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Patent # Description
US-6,901,118 Enhanced viterbi decoder for wireless applications
A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric...
US-6,900,969 ESD protection with uniform substrate bias
Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry...
US-6,900,918 Torsionally hinged devices with support anchors
A functional surface, such as a reflective surface, is supported by a pair of torsional hinges for pivoting about a first axis which in turn is supported by a...
US-6,900,910 Modulo addressing for look up table screening for printing files in a page description language
This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time...
US-6,900,701 Automatic detection, selection and configuration of clock oscillator circuitry
Oscillator circuitry on an integrated circuit automatically detects the presence or absence of an external resistor which is used to bias and set the frequency...
US-6,900,656 Method of testing an integrated circuit and an integrated circuit test apparatus
A method of testing an Integrated Circuit (IC) and an IC test apparatus is provided. In one embodiment, the method of testing includes (1) applying a voltage to...
US-6,900,534 Direct attach chip scale package
A reliable, chip scale or flip chip semiconductor device which can be directly attached to a PC board without the use of an underfill material to absorb stress...
US-6,900,127 Multilayer integrated circuit copper plateable barriers
A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100)...
US-6,900,123 BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control
A BARC etch comprises a selective etch chemistry in combination with a high-polymerizing gas for CD control. The BARC etch may be used in a via-first dual...
US-6,900,101 LDMOS transistors and methods for making the same
LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between...
US-6,898,849 Method for controlling wire balls in electronic bonding
A method for forming a substantially spherical free air ball on a fine non-oxidizable wire in a computerized bonder, which has a computerized flame-off (EFO)...
US-6,898,766 Simplifying integrated circuits with a common communications bus
When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage....
US-6,898,749 IC with cache bit memory in series with scan segment
Low power delay test capabilities in Scan and Scan-BIST architectures occur by inserting a first cache bit memory between the scan input lead and the serial...
US-6,898,678 Shared memory with programmable size
A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access...
US-6,898,544 Instruction register and access port gated clock for scan cells
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for...
US-6,898,534 DC measurement method and system using sigma-delta modulation pattern
Disclosed are methods, systems, and algorithms for accurately measuring a DC voltage signal (V.sub.in) using a sigma-delta modulator (36). The preferred...
US-6,898,418 Method of and apparatus for implementing adaptive downstream modulation in a fixed wireless communication system
Available quadrature amplitude modulation ("QAM") carriers transmittable by a base station to customer sites are substantially equally divided among the sites...
US-6,898,254 Turbo decoder stopping criterion improvement
A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a...
US-6,898,068 Dual mask capacitor for integrated circuits
An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor...
US-6,898,019 Pulse width modulation sequence generation
An electronic method for addressing and synchronizing a spatial light modulator (SLM) device when used with color scrolling recovery (SCR) illumination. This...
US-6,897,991 DMD pixel with small-rotated-moved via2 to reduce beam-electrode shorts
A digital micromirror device with an optimized beam dimple formed over the via2 to provide process margin by increasing the clearance between the beam and the...
US-6,897,794 All-analog calibration of sting-DAC linearity: application to high voltage processes
A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of...
US-6,897,731 Method and circuit for overload recovery of an amplifier
A method and circuit for providing a faster overload recovery time for an amplifier circuit is provided. An overload recovery circuit is configured to reduce...
US-6,897,701 Method and structure for improving the linearity of MOS switches
A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a...
US-6,897,694 Circuitry for reducing the skew between two signals
An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block...
US-6,897,681 Time division multiplexed serial bus with increased bandwidth
The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to...
US-6,897,670 Parallel integrated circuit test apparatus and test method
A test apparatus (400) comprising a single handler (404) is coupled to a first tester (436) and second tester (408), wherein the first (436) and second (408)...
US-6,897,637 Low drop-out voltage regulator with power supply rejection boost circuit
A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted...
US-6,897,516 Flash memory array structure and method of forming
A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the...
US-6,897,505 On-chip capacitor
An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the ...
US-6,897,113 Single poly EEPROM with improved coupling ratio
A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well...
US-6,897,105 Method of forming metal oxide gate structures and capacitor electrodes
An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method...
US-6,896,588 Chemical mechanical polishing optical endpoint detection
Light is incident on a semiconductor wafer polish surface and an adjacent reference surface (80). The reflected light from each surface is detected by a detector...
US-6,895,494 Sub-pipelined and pipelined execution in a VLIW
A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch...
US-6,895,493 System and method for processing data in an integrated circuit environment
A method for processing data is provided that includes storing a write operation in a store buffer that indicates a first data element is to be written to a...
US-6,895,479 Multicore DSP device having shared program memory with conditional write protection
A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal...
US-6,895,465 SDRAM with command decoder, address registers, multiplexer, and sequencer
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,895,344 Extracting resistances for a substrate network
Determining a substrate resistance network includes receiving a description of a substrate network including nodes. Elements of the substrate network are...
US-6,895,109 Apparatus and method for automatically detecting defects on silicon dies on silicon wafers
An apparatus and method for automatically detecting defects on silicon dies on silicon wafers comprising a silicon wafer acquisition system (30) and a computer...
US-6,895,093 Acoustic echo-cancellation system
A multi-channel acoustic cancellation system 40 with, for example, stereo speakers and a pair of microphones in the transmitting and receiving rooms (11 and 21)...
US-6,895,090 Pseudo-noise sequence with insertion having variant length and position
An augmented pseudo-noise sequence (10) is generated from a two or more pseudo-noise sequences, using LFSRs or other such devices. A segment (16) of a one...
US-6,894,853 Stress relieved frame
An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the...
US-6,894,627 Increasing the SNR of successive approximation type ADCs without compromising throughput performance substantially
When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and...
US-6,894,548 Circuit for modifying a clock signal to achieve a predetermined duty cycle
The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the...
US-6,894,542 Comparator with hysteresis
A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second...
US-6,894,503 Preconditional quiescent current testing of a semiconductor device
A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor...
US-6,894,374 Semiconductor package insulation film and manufacturing method thereof
An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation film 10 is provided with rows of...
US-6,894,366 Bipolar junction transistor with a counterdoped collector region
An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the...
US-6,894,318 Diode having a double implanted guard ring
The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the...
US-6,894,308 IC with comparator receiving expected and mask data from pads
Test circuits located on semiconductor die enable a tester to scan test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to...
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