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| Patent # | Description |
|---|---|
| US-7,183,823 |
Method of generating a pulsed output signal from a periodic ramp signal
and a reference voltage, and a switch... In the proposed method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, the linear range of duty cycles of the pulsed... |
| US-7,183,793 |
Systems and methods for reducing electromagnetic emissions from a
controller area network transceiver Systems are provided for reducing electromagnetic emissions from a controller area network transceiver. A driver circuit is operative to transmit communications... |
| US-7,183,789 |
Comparing on die response and expected response applied to outputs A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response... |
| US-7,183,657 |
Semiconductor device having resin anti-bleed feature A device and a method for controlling resin bleed, the device comprising a substrate having a surface, wherein an interior region, a peripheral region, and an... |
| US-7,183,602 |
Ferroelectric capacitor hydrogen barriers and methods for fabricating the
same Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C.sub.FE) from hydrogen diffusion in semiconductor devices (102),... |
| US-7,183,570 |
IC with comparator receiving expected and mask data from pads Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the... |
| US-7,183,221 |
Method of fabricating a semiconductor having dual gate electrodes using a
composition-altered metal layer Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the... |
| US-7,183,187 |
Integration scheme for using silicided dual work function metal gates The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor... |
| US-7,183,165 |
Reliable high voltage gate dielectric layers using a dual nitridation
process Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor... |
| US-7,182,469 |
High contrast projection A method and system for improving the contrast ratio of a projected image. An asymmetric aperture stop improves the contrast ratio of a projected image. Using... |
| US-7,181,676 |
Layered decoding approach for low density parity check (LDPC) codes A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the... |
| US-7,181,192 |
Handheld portable automatic emergency alert system and method In one embodiment, an automated emergency alert system includes a handheld portable communication device operable to initiate communication over a wireless... |
| US-7,181,167 |
High data rate closed loop MIMO scheme combining transmit diversity and
data multiplexing Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise... |
| US-7,181,073 |
Image coding using embedded zerotree patterns and bitplanes An image coding method using wavelet decomposition and coding clusters of four-children coefficients bitplane-wise including value-bits for significance and... |
| US-7,181,065 |
Enhanced color correction circuitry capable of employing negative RGB
values Disclosed is a system for adjusting a plurality of component color signals for expanded color gamut displays. The disclosed system comprises an input for... |
| US-7,180,971 |
Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode... |
| US-7,180,965 |
Phase estimation and compensation in orthogonal frequency division
multiplex (OFDM) systems Methods are presented for phase estimation and compensation in Orthogonal Frequency Division Multiplex systems. The methods include the step of extracting... |
| US-7,180,955 |
Parallel concatenated trellis-coded modulation with asymmetric signal
mapping Parallel concatenated trellis-coding modulation is accomplished by producing coded bits (21) from uncoded bits and also producing an interleaved version (22) of... |
| US-7,180,456 |
Antennas supporting high density of wireless users in specific directions A low cost antenna in a base station suitable for deployment where high density of wireless users are present in specific directions (e.g., cross roads in urban... |
| US-7,180,319 |
Selecting groups of dies for wafer testing Integrated circuit die on wafer are tested individually, without probing any of the die, using circuitry (TC1 8, BC1 8, LR1 8, RR1 8, PA1 PA4) provided on the... |
| US-7,180,275 |
DC-DC high frequency boost converter A DC-DC high frequency boost converter with a supply voltage input (110), a boosted voltage output (112), a series circuit of an inductor (114) and a rectifying... |
| US-7,180,208 |
Switch structure for reduced voltage fluctuation in power domains and
sub-domains System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a... |
| US-7,180,159 |
Bipolar transistor having base over buried insulating and polycrystalline
regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite... |
| US-7,180,141 |
Ferroelectric capacitor with parallel resistance for ferroelectric memory Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge... |
| US-7,179,751 |
Hydrogen plasma photoresist strip and polymeric residue cleanup process
for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position... |
| US-7,179,747 |
Use of supercritical fluid for low effective dielectric constant
metallization An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step... |
| US-7,179,738 |
Semiconductor assembly having substrate with electroplated contact pads An apparatus comprising an insulating substrate (101) having first and second surfaces (101a, 101b) and a plurality of metal-filled vias (102) extending from the... |
| US-7,179,696 |
Phosphorus activated NMOS using SiC process A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate... |
| US-7,178,138 |
Method and tool for verification of algorithms ported from one instruction
set architecture to another The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set... |
| US-7,178,080 |
Hardware-efficient low density parity check code for digital
communications A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The... |
| US-7,177,965 |
Linking addressable shadow port and protocol for serial bus networks Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of... |
| US-7,177,876 |
Speculative load of look up table entries based upon coarse index
calculation in parallel with fine index... A computer implemented method accesses data in a look up table via an index divided into a coarse index and a fine index. The method calculates the coarse index... |
| US-7,177,805 |
Simplified noise suppression circuit A system for reducing noise in an acoustical signal comprises a sampler (104) for obtaining discrete samples of the acoustical signal, an analog to digital... |
| US-7,177,801 |
Speech transfer over packet networks using very low digital data
bandwidths A method of communicating speech across a communication link using very low digital data bandwidth is disclosed, having the steps of: translating speech into... |
| US-7,177,772 |
System and method for generating and measuring noise parameters A method for measuring noise parameters includes generating a noise signal at a noise source. The noise signal includes a first input signal at a first frequency... |
| US-7,177,651 |
System and method for the exchange of location information in a telephone
network A wireless communications system is presented where a mobile station is able to automatically determine its proximity to a second mobile station or landline... |
| US-7,177,613 |
Reducing noise and distortion in a receiver system A receiver, implemented with low noise and low distortion, to process an input signal containing signals of interest and unwanted interference signal. In an... |
| US-7,177,611 |
Hybrid control of phase locked loops A hybrid digital and analog phase locked loop. A voltage controlled oscillator is provided, having a fine tune input, a coarse tune input and an output. A... |
| US-7,177,418 |
Power efficient ADSL central office downstream class G power switch Systems and methods are provided for switching between power supply rail voltages for a differential driver device of a class G amplifier device. The amplifier... |
| US-7,177,401 |
TTY communication over packet networks A system to enable TTY communication between a legacy TTY phone and an IP phone over a packet network using a TTY relay protocol established between the IP phone... |
| US-7,177,306 |
Calculation of clock skew using measured jitter buffer depth A system and method to measure the clock skew between transmitting and receiving devices operating with independent clock sources over a packet network is... |
| US-7,176,985 |
Clamping circuit for video signals An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied... |
| US-7,176,821 |
Reduced area digital sigma-delta modulator A digital sigma-delta modulator requiring minimal die area and dissipating minimal power is formed with a plurality of integration stages coupled in tandem... |
| US-7,176,815 |
Video coding with CABAC Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus... |
| US-7,176,760 |
CMOS class AB folded cascode operational amplifier for high-speed
applications An operational amplifier (1A or 1B) includes a translinear transconductance stage (2B or 2C) receiving an input signal (Vin) of the operational amplifier and... |
| US-7,176,749 |
Avoiding excessive cross-terminal voltages of low voltage transistors due
to undesirable supply-sequencing in... Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient... |
| US-7,176,742 |
Bootstrapped switch with an input dynamic range greater than supply
voltage A bootstrapping circuit capable of sampling inputs beyond a supply voltage which includes a bootstrapped switch coupled between an input node and an output node,... |
| US-7,176,726 |
Integrated loss of signal detection with wide threshold range and precise
hysteresis A loss-of-signal (LOS) detector includes a variable gain amplifier with an input receiving an input signal, a threshold comparator with a first input receiving a... |
| US-7,176,091 |
Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer... |
| US-7,176,076 |
Semiconductor CMOS devices and methods with NMOS high-k dielectric present
in core region that mitigate damage... The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS... |
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