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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-6,998,275 |
Hydrogen-less CVD TiN process for FeRAM VIA0 barrier application The present invention is directed to a method of forming a diffusion barrier layer for a FeRAM capacitor, which includes depositing a chemical vapor deposited... |
| US-6,998,221 |
Method for forming a via in a substrate The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention,... |
| US-6,997,192 |
Control of dissolved gas levels in deionized water An embodiment of the invention is an apparatus having a cleaning tank 2, a megasonic energy source 3, and an intake pipe 6 where a membrane contactor 9 is... |
| US-6,996,787 |
Integrated circuit cells According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a... |
| US-6,996,765 |
Turbo decoder prolog reduction This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric... |
| US-6,996,761 |
IC with protocol selection memory coupled to serial scan path A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register... |
| US-6,996,747 |
Program counter trace stack, access port, and serial scan path A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor... |
| US-6,996,735 |
Apparatus for alignment of data collected from multiple pipe stages with
heterogeneous retention policies in an... A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory... |
| US-6,996,730 |
Adjusting voltage supplied to a processor in response to clock frequency A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit is provided. A request signal is sent to the clock, and in... |
| US-6,996,683 |
Cache coherency in a multi-processor system A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the... |
| US-6,996,231 |
Step size convergence control A method of converging a step size control for an adaptive filter of a communication channel including: (1) initializing a nominal step size value and a penalty... |
| US-6,996,162 |
Correlation using only selected chip position samples in a wireless
communication system A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises a first synchronization... |
| US-6,996,118 |
Central office line card with code recognition for increasing data rates
over PSTN A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152)... |
| US-6,996,091 |
Central office line card with code recognition for increasing data rates
over PSTN A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152)... |
| US-6,996,015 |
First-in first-out memory system with single bit collision detection An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises... |
| US-6,995,810 |
Method and system for automated convergence and focus verification of
projected images A method and system that objectively measures the convergence and focus of a 2 or 3 spatial light modulator (SLM) projection display. The system uses five (5)... |
| US-6,995,647 |
Low current electric motor protector A low current motor protector (10, 10') has an oblong metal housing (12) defining a switch chamber and formed with an open end. The housing has opposing flange... |
| US-6,995,624 |
Oscillator circuit having a copy of the activating component Oscillator circuit with an LC resonant circuit 1, an activating component 2 connected to the LC resonant circuit 1, which serves to compensate for the losses... |
| US-6,995,599 |
Cross-conduction blocked power selection comparison/control circuitry with
NTC (negative temperature... Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array... |
| US-6,995,598 |
Level shifter circuit including a set/reset circuit The present invention discloses a level shifter circuit (20) comprising a serially coupled first device (M3) and second device (M5), a serially coupled third... |
| US-6,995,587 |
Low voltage low power bandgap circuit Disclosed are methods and circuits for providing a bandgap reference in an electronic circuit having a supply voltage and ground. The methods include steps for... |
| US-6,995,537 |
Closed-loop control system to mitigate PWM switching noise One aspect of the present invention provides a motor control system that includes a linear control system operative, in a linear mode, to provide a plurality of... |
| US-6,995,483 |
Synchronous buck and boost regulator power reduction circuit using high
side sensing A synchronous DC-DC regulator, adapted to receive a high side pulsed signal and a low side pulsed signal that is substantially the inverse of the high side... |
| US-6,995,097 |
Method for thermal nitridation and oxidation of semiconductor surface An embodiment of the instant invention is a method of forming a dielectric layer on a silicon-containing structure, the method comprising the steps of: providing... |
| US-6,995,088 |
Surface treatment of copper to improve interconnect formation The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a... |
| US-6,995,042 |
Method for fabricating preplated nickel/palladium and tin leadframes A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a... |
| US-6,995,037 |
Structure and method of high performance two layer ball grid array
substrate A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an... |
| US-6,994,544 |
Wafer scale thermal stress fixture and method A fixture for supporting a plurality of semiconductor chips during the thermal cycling of the chips, including a fluid-permeable bottom screen, a... |
| US-6,993,736 |
Pending bug monitors for efficient processor development and debug This invention addresses difficult issues encountered in simulations and design verification efforts on complex microprocessor/digital signal processor devices.... |
| US-6,993,704 |
Concurrent memory control for turbo decoders The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an... |
| US-6,993,702 |
Radix-N architecture for deinterleaver-depuncturer block A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed... |
| US-6,993,546 |
Quantized nonlinear scaler A method of providing a low cost quantized nonlinear scaler for a continuous curve includes the steps of providing a quantized coefficient table representing an... |
| US-6,993,099 |
Communications receiver architectures and algorithms permitting hardware
adjustments for optimizing performance A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's... |
| US-6,993,095 |
Phase-locked loop initialization via curve-fitting A method and apparatus for accurately estimating the carrier frequency offset and the carrier phase offset of a digitally modulated signal using a signal... |
| US-6,992,679 |
Hardware display rotation A visual display is provided on a data processing apparatus by storing and retrieving display information. The display information is stored by receiving write... |
| US-6,992,608 |
Current-steering digital-to-analog converter having a minimum charge
injection latch A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of... |
| US-6,992,606 |
Method and circuit for multi-standard sigma-delta modulator System and method for a multi-standard sigma-delta modulator. A preferred embodiment comprises an integrator coupled to a signal input, wherein the integrator is... |
| US-6,992,523 |
Low voltage current monitoring circuit A current monitor (360) having a high performance, simple, and cost effective design that is independent of process, temperature and voltage is disclosed herein.... |
| US-6,992,463 |
Battery protection circuit A protection of battery system having battery cells Cell1.about.Cell3, FET switches SW1, SW2 that are connected to the high-side path and control on/off state of... |
| US-6,992,422 |
Position sensor for a pivoting platform A position sensor for a pivoting platform which has a first portion that flexes when the platform pivots and a second portion of the platform that is rigid,... |
| US-6,992,380 |
Package for semiconductor device having a device-supporting polymeric
material covering a solder ball array area A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond... |
| US-6,992,375 |
Anchor for device package An anchor to hold getter materials in place within a micromechanical device package substrate. First and second cavity faces define an anchor cavity and... |
| US-6,992,023 |
Method and system for drying semiconductor wafers in a spin coating
process The invention provides methods and apparatus for drying the backside of semiconductor wafers in a spin-coating environment. Solvent is evaporatively dried from a... |
| US-6,990,657 |
Shared software breakpoints in a shared memory system The invention relates to a method for maintaining coherency of software breakpoints in shared memory when debugging a multiple processor system. Using this... |
| US-6,990,620 |
Scanning a protocol signal into an IC for performing a circuit operation A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register... |
| US-6,990,570 |
Processor with a computer repeat instruction A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The... |
| US-6,990,549 |
Low pin count (LPC) I/O bridge A low pin count (LPC) input/output (I/O) bridge device and method for a portable computer having a plurality of legacy ports and a docking connector. The LPC I/O... |
| US-6,990,519 |
Use of a directed acyclic organization structure for selection and
execution of consistent subsets of rewrite rules The present invention discloses the use of a hand-held calculator programmed to teach subject matter such as mathematics in a manner that emulates traditional... |
| US-6,990,343 |
Context block leasing for fast handoffs The roaming of a wireless device 115 extends the effective range of a wireless network 100 by passing a device 115 between access points as the device leaves the... |
| US-6,990,157 |
All-digital FSK demodulation with selectable data rate and adjustable
resolution All-digital FSK demodulation can be accomplished by producing in response to a received IF signal digital information (22) indicative of a frequency of the IF... |
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