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| Patent # | Description |
|---|---|
| US-6,921,721 |
Post plasma clean process for a hardmask The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes... |
| US-6,921,703 |
System and method for mitigating oxide growth in a gate dielectric Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in... |
| US-6,921,701 |
Method of manufacturing and structure of semiconductor device (DEMOS) with
field oxide structure A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of... |
| US-6,921,680 |
Method and apparatus for MEMS device nebulizer lubrication system A nebulization system, which creates a uniform fog of tiny suspended liquid droplets, to lubricate the surfaces of MEMS devices. These droplets fall over the... |
| US-6,920,572 |
Unanimous voting for disabling of shared component clocking in a multicore
DSP device A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed... |
| US-6,920,471 |
Compensation scheme for reducing delay in a digital impedance matching
circuit to improve return loss A simple, power efficient and inexpensive digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss. The... |
| US-6,920,416 |
Electronic systems testing employing embedded serial scan generator An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic... |
| US-6,920,220 |
Pre-zero crossing signal generator for sinusoidal voltages with DC offsets
such as telephone ring voltages A circuit for closing a relay when an active AC voltage connected to one of the contacts of the relay is approximately zero volts includes a monitoring circuit... |
| US-6,920,193 |
Wireless receiver using noise levels for combining signals having spatial
diversity A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain... |
| US-6,919,870 |
Driving circuit The objective of this invention is to compensate or avoid the influence of offset in an easy and efficient manner, to correctly match the voltage of the output... |
| US-6,919,753 |
Temperature independent CMOS reference voltage circuit for low-voltage
applications A temperature independent CMOS reference voltage circuit includes a CMOS current mirror circuit containing first and second CMOS transistors of a first polarity.... |
| US-6,919,751 |
Dynamic receiver clamp that is enabled during periods in which overshoot is
likely A dynamic clamp 200 selectively clamps overshoot on a signal line 100 when overshoot is likely, while not clamping the received signal at times when overshoot is... |
| US-6,919,727 |
Accurate time measurement system circuit and method Disclosed is a method of measuring the time signal of an electronic device including steps for measuring a true signal and an inverted signal. The measured true... |
| US-6,919,629 |
Method and system for integrated circuit packaging According to one embodiment of the invention, a mold tool for packaging integrated circuits includes a first mold press die including a first non-planar surface... |
| US-6,919,605 |
Integrated circuit MOS transistor with reduced drain and source resistance A gate structure (30) is formed on a semiconductor (10). Source and drain extension regions (130) are formed in the semiconductor (10) adjacent to the gate... |
| US-6,919,603 |
Efficient protection structure for reverse pin-to-pin electrostatic
discharge An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a... |
| US-6,919,251 |
Gate dielectric and method CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a... |
| US-6,919,233 |
MIM capacitors and methods for fabricating same Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling... |
| US-6,919,219 |
Photon-blocking layer An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the... |
| US-6,918,025 |
IC with wait state registers A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a... |
| US-6,918,018 |
64-bit single cycle fetch scheme for megastar architecture The 64-bit single cycle fetch method described here relates to a specific `megastar` core processor employed in a range of new digital signal processor devices.... |
| US-6,917,597 |
System and method of communication using transmit antenna diversity based
upon uplink measurement for the TDD... A system and method of data communication uses variable transmit antenna delays based on uplink measurements for the time division duplex (TDD) mode of WCDMA... |
| US-6,917,503 |
Programmable current limiting using a shunt resistor An overcurrent protection circuit using a shunt resistor and the voltage drop across a switch to program a user-defined current limiting level. This protects the... |
| US-6,917,484 |
Damping resistor boost writer architecture A write driver apparatus and corresponding method for an inductive head element (20) in a magnetic storage medium, such as a hard disk drive, having an H-bridge... |
| US-6,917,467 |
Optical amplifier A programmable amplifier 100 operable to independently adjust the amplification given to various optical signals passing through an optical fiber. An input... |
| US-6,917,461 |
Laminated package A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. One embodiment provides a method... |
| US-6,917,311 |
Orthogonal preamble encoder, method of encoding orthogonal preambles and
multiple-input, multiple-output... For use with a multiple-input, multiple-output (MIMO) transmitter, an orthogonal preamble encoder, a method of encoding orthogonal preambles and a communication... |
| US-6,917,257 |
Apparatus and method for equalizing received signals An apparatus for equalizing input signals including high and low frequency component signals received at an locus includes: (a) a first signal amplifying circuit... |
| US-6,917,240 |
Reconfigurable topology for switching and charge pump negative polarity
regulators A configurable voltage regulator (128) operable in either of two selectable modes or topologies is disclosed. In one disclosed embodiment, the voltage regulator... |
| US-6,917,223 |
Gaussian noise generator A signal generator (10). The signal generator comprises circuitry (20) for producing at least a first input noise signal (N.sub.1), wherein the first input noise... |
| US-6,917,098 |
Three-level leadframe for no-lead packages A semiconductor device (700) having a leadframe with a first plurality of segments (110) having a narrow end portion (111) in a first horizontal plane (211) and... |
| US-6,917,093 |
Method to form shallow trench isolation with rounded upper corner for
advanced semiconductor circuits A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a... |
| US-6,917,084 |
Interdigitated layout methodology for amplifier and H-bridge output stages A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an... |
| US-6,916,689 |
Plastic chip-scale package having integrated passive components A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic... |
| US-6,915,566 |
Method of fabricating flexible circuits for integrated circuit
interconnections A method for the fabrication of a double-sided electrical interconnection flexible circuit (200) particularly useful as a substrate for an area array integrated... |
| US-6,915,478 |
Method and apparatus for computing Reed-Solomon error magnitudes In a Reed-Solomon decoder, error magnitudes are determined from a root matrix and a syndrome vector. The root matrix is triangularized (60) using recursive... |
| US-6,915,459 |
Active failsafe detection for differential receiver circuits The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal (11) is... |
| US-6,915,416 |
Apparatus and method for microcontroller debugging Apparatus and method for microcontroller debugging. A preferred embodiment microcontroller integrated circuit comprises debug circuitry on the integrated... |
| US-6,915,360 |
Cell buffering system with priority cache in an ATM system The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A... |
| US-6,915,247 |
Computer system The objective of the invention is to be able to switch between execution and cancellation of copy protection at any time in a simplified structure. The switching... |
| US-6,914,948 |
Media noise post-processor with varying threshold A post-processing method and circuit (30) for correcting media noise errors and producing a corrected recovered data output signal (49) is disclosed for use in a... |
| US-6,914,550 |
Differential pipelined analog to digital converter with successive
approximation register subconverter stages... Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer... |
| US-6,914,549 |
Reconfigurable analog-to-digital converter Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control... |
| US-6,914,546 |
Device and method of digital gain programming using sigma-delta modulator A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set... |
| US-6,914,486 |
System and method for improved bias matching Systems and methods to improve bias matching (e.g., for a current feedback amplifier) are described. A compensation signal is combined with one or more bias... |
| US-6,914,447 |
High activity, spatially distributed radiation source for accurately
simulating semiconductor device radiation... The present invention pertains to radiation sources that mimic radiation environment(s) encountered by packaged semiconductor devices. The sources are suitable... |
| US-6,914,332 |
Flip-chip without bumps and polymer for board assembly A semiconductor chip having a planar active surface including an integrated circuit protected by an inorganic overcoat; the circuit has metallization patterns... |
| US-6,914,004 |
Method for via etching in organo-silica-glass According to one embodiment of the invention, a method for via etching in a dielectric material includes providing a wafer (200) having a substrate (202), an... |
| US-6,913,980 |
Process method of source drain spacer engineering to improve transistor
capacitance A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are... |
| US-6,913,527 |
Edge-sealed pad for CMP process The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process... |
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