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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-6,982,615 |
System and method for threaded plunger assembly A system and method for a plunger assembly includes a tuning slug with a bore in the stem, a tuning screw rotatably disposed in the stem, and a coupling assembly... |
| US-6,982,610 |
Termination impedance tuning circuit An impedance adjustment system comprising current source, a first series and a second series connected string of predetermined number of resistors, a first and... |
| US-6,982,588 |
Inverse function method for semiconductor mixer linearity enhancement The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a... |
| US-6,982,448 |
Ferroelectric capacitor hydrogen barriers and methods for fabricating the
same Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C.sub.FE) from hydrogen diffusion in semiconductor devices (102),... |
| US-6,982,400 |
Electrical heater apparatus A self retaining crankcase heater (10) has a tubular casing (12) of relatively flexible, thermally conductive material in which is received a PTC element (16),... |
| US-6,982,377 |
Time-scale modification of music signals based on polyphase filterbanks
and constrained time-domain processing A time scale modification method employs separate bands obtained through an analysis polyphase filter bank with separate time-scale modification processing for... |
| US-6,981,204 |
Programmable glitch filter for an asynchronous data communication interface An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels... |
| US-6,981,190 |
Controlling the content of specific desired memory elements when testing
integrated circuits using sequential... A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test... |
| US-6,981,178 |
Separation of debug windows by IDS bit A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon... |
| US-6,981,130 |
Forwarding the results of operations to dependent instructions more quickly
via multiplexers working in parallel Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective ... |
| US-6,980,952 |
Source normalization training for HMM modeling of speech A maximum likelihood (ML) linear regression (LR) solution to environment normalization is provided where the environment is modeled as a hidden (non-observable)... |
| US-6,980,950 |
Automatic utterance detector with high noise immunity An utterance detector for speech recognition is described. The detector consists of two components. The first part makes a speech/non-speech decision for each... |
| US-6,980,588 |
Apparatus for handling high speed data communication signals and method for
manufacture thereof An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at... |
| US-6,980,459 |
Non-volatile SRAM A SRAM cell wherein the pull up load of the cell is inherent ferroelectric leakage. The power down writeback may include boosting the word line. The power down... |
| US-6,980,407 |
Arc detection apparatus and method Current flowing through a load is monitored by a transformer (Tr1) having a small mutual inductance. The secondary coil is shorted through a rectifier circuit to... |
| US-6,980,144 |
Method for reducing DAC resolution in multi-bit sigma delta analog-to
digital converter (ADC) A method for reducing the resolution of a digital-to-analog converter in a multi-bit sigma-delta ADC is described. With the addition of digital sigma-delta... |
| US-6,980,055 |
CMOS differential buffer circuit The present invention pertains to a MOS type differential buffer circuit. The buffer proposed herein utilizes capacitive coupling to apply small AC signals to an... |
| US-6,979,908 |
Input/output architecture for integrated circuits with efficient
positioning of integrated circuit elements A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a... |
| US-6,979,899 |
System and method for high performance heat sink for multiple chip devices A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die... |
| US-6,979,788 |
Electrical switch system responsive to gear selection of vehicular
transmission An electrical switch system (10) for use with a motor vehicle transmission has a movable contact assembly (16) mounted on an insulative base member (14) in turn... |
| US-6,979,648 |
Method for BARC over-etch time adjust with real-time process feedback A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The... |
| US-6,979,647 |
Method for chemical etch control of noble metals in the presence of less
noble metals A method for preparing a bonding pad on an integrated circuit wafer by the steps of depositing a conductive seed layer (104) on the bonding pad; depositing a... |
| US-6,979,637 |
Method and structure for controlling surface properties of dielectric
layers in a thin film component for... A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming... |
| US-6,979,623 |
Method for fabricating split gate transistor device having high-k
dielectrics Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses... |
| US-6,979,615 |
System and method for forming a semiconductor with an analog capacitor
using fewer structure steps A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the... |
| US-6,978,389 |
Variable clocking in an embedded symmetric multiprocessor system In multiprocessor systems the task of holding power dissipation to its lowest possible level is challenging. This invention permits reduced power dissipation by... |
| US-6,978,387 |
Hold time latch with decreased percharge node voltage leakage A dynamic logic hold time latch (20). The latch comprises a first phase circuit (12') operable in a precharge phase and an evaluate phase and a second phase... |
| US-6,977,910 |
Power control with space time transmit diversity A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a... |
| US-6,977,691 |
System for nonlinear viewing of television show segments A system for nonlinear viewing of television show segments is provided by transmitting a main signal and an ancillary signal. The ancillary signal is a short... |
| US-6,977,605 |
Dummy delay line based DLL and method for clocking in pipeline ADC A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay... |
| US-6,977,547 |
Minimizing changes in the amplification factor of an amplification circuit
during operation A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification... |
| US-6,977,542 |
Adjusting the trans-conductance of a filter A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having... |
| US-6,977,488 |
DC-DC converter A DC--DC converter can supply a stable output voltage from an input voltage with the power supply voltage varying along with the supply of the power and can... |
| US-6,977,443 |
Substrate for carrying a semiconductor chip and semiconductor device using
same The objective of this invention is to provide a type of substrate for carrying a semiconductor chip that can increase the arrangement density of lands, and a... |
| US-6,977,437 |
Method for forming a void free via A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier... |
| US-6,977,429 |
Manufacturing system and apparatus for balanced product flow with
application to low-stress underfilling of... A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this... |
| US-6,977,196 |
Micro-electromechanical switch fabricated by simultaneous formation of a
resistor and bottom electrode The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical... |
| US-6,977,191 |
Apparatus for and method of packaging semiconductor devices A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one... |
| US-6,975,980 |
Hierarchical linking module connection to access ports of embedded cores An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports... |
| US-6,975,920 |
In-situ randomization and recording of wafer processing order at process
tools Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing... |
| US-6,975,722 |
Dual echo canceller with fast reflector identification An echo canceller, which includes, receives and sends paths connected to standard telecommunication interfaces, a non adaptive filter with filter reflection... |
| US-6,975,684 |
Dynamic slave frequency selection for improving uplink frequency hopping
wireless communications In wireless communications between a frequency hopping master device (M) and a frequency hopping slave device (S.sub.1), the slave-to-master transmission... |
| US-6,975,629 |
Processing packets based on deadline intervals A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of... |
| US-6,975,473 |
Power efficient overshoot protection during an operating mode transition A system and method provide overshoot protection to facilitate driving a load by output circuitry in response to a transition from a first operating mode to a... |
| US-6,975,354 |
Digital still camera color filter array interpolation system and method Digital Still Camera (DSC) includes separate preview engine, burst mode compression/decompression engine, image pipeline, CCD plus CCD controller, and memory... |
| US-6,975,255 |
Random interleaving dither for sigma-delta analog-to-digital converters A dithering method is provided for sigma-delta converters in a deep-submicron process. The dither is a random interleaving of quantizer thresholds levels. The... |
| US-6,975,170 |
Adaptive amplifier output common mode voltage adjustment The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential... |
| US-6,975,153 |
Low power input with hysteresis circuit and methods therefor A low power input with hysteresis circuit provides input hysteresis (for instance, from supply voltage ranges of 0.8 volt to 5.5 volts), while reducing the... |
| US-6,975,143 |
Static logic design for CMOS A static logic circuit with a pull-up network (155) and a pull-down network (160). The network is fabricated on SOI substrates and the pull-up network comprises... |
| US-6,975,099 |
Efficient frequency compensation for linear voltage regulators The present application describes a frequency compensation scheme for a linear voltage regulator circuit, or its special case, a low-drop out voltage regulator... |
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