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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-6,898,068 |
Dual mask capacitor for integrated circuits An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor... |
| US-6,898,019 |
Pulse width modulation sequence generation An electronic method for addressing and synchronizing a spatial light modulator (SLM) device when used with color scrolling recovery (SCR) illumination. This... |
| US-6,897,991 |
DMD pixel with small-rotated-moved via2 to reduce beam-electrode shorts A digital micromirror device with an optimized beam dimple formed over the via2 to provide process margin by increasing the clearance between the beam and the... |
| US-6,897,794 |
All-analog calibration of sting-DAC linearity: application to high voltage
processes A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of... |
| US-6,897,731 |
Method and circuit for overload recovery of an amplifier A method and circuit for providing a faster overload recovery time for an amplifier circuit is provided. An overload recovery circuit is configured to reduce... |
| US-6,897,701 |
Method and structure for improving the linearity of MOS switches A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a... |
| US-6,897,694 |
Circuitry for reducing the skew between two signals An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block... |
| US-6,897,681 |
Time division multiplexed serial bus with increased bandwidth The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to... |
| US-6,897,670 |
Parallel integrated circuit test apparatus and test method A test apparatus (400) comprising a single handler (404) is coupled to a first tester (436) and second tester (408), wherein the first (436) and second (408)... |
| US-6,897,637 |
Low drop-out voltage regulator with power supply rejection boost circuit A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted... |
| US-6,897,516 |
Flash memory array structure and method of forming A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the... |
| US-6,897,505 |
On-chip capacitor An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the ... |
| US-6,897,113 |
Single poly EEPROM with improved coupling ratio A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well... |
| US-6,897,105 |
Method of forming metal oxide gate structures and capacitor electrodes An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method... |
| US-6,896,588 |
Chemical mechanical polishing optical endpoint detection Light is incident on a semiconductor wafer polish surface and an adjacent reference surface (80). The reflected light from each surface is detected by a detector... |
| US-6,895,494 |
Sub-pipelined and pipelined execution in a VLIW A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch... |
| US-6,895,493 |
System and method for processing data in an integrated circuit environment A method for processing data is provided that includes storing a write operation in a store buffer that indicates a first data element is to be written to a... |
| US-6,895,479 |
Multicore DSP device having shared program memory with conditional write
protection A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal... |
| US-6,895,465 |
SDRAM with command decoder, address registers, multiplexer, and sequencer A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit... |
| US-6,895,344 |
Extracting resistances for a substrate network Determining a substrate resistance network includes receiving a description of a substrate network including nodes. Elements of the substrate network are... |
| US-6,895,109 |
Apparatus and method for automatically detecting defects on silicon dies on
silicon wafers An apparatus and method for automatically detecting defects on silicon dies on silicon wafers comprising a silicon wafer acquisition system (30) and a computer... |
| US-6,895,093 |
Acoustic echo-cancellation system A multi-channel acoustic cancellation system 40 with, for example, stereo speakers and a pair of microphones in the transmitting and receiving rooms (11 and 21)... |
| US-6,895,090 |
Pseudo-noise sequence with insertion having variant length and position An augmented pseudo-noise sequence (10) is generated from a two or more pseudo-noise sequences, using LFSRs or other such devices. A segment (16) of a one... |
| US-6,894,853 |
Stress relieved frame An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the... |
| US-6,894,627 |
Increasing the SNR of successive approximation type ADCs without
compromising throughput performance substantially When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and... |
| US-6,894,548 |
Circuit for modifying a clock signal to achieve a predetermined duty cycle The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the... |
| US-6,894,542 |
Comparator with hysteresis A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second... |
| US-6,894,503 |
Preconditional quiescent current testing of a semiconductor device A method for testing a semiconductor device is included where sleep mode commands associated with the semiconductor device are generated. The semiconductor... |
| US-6,894,374 |
Semiconductor package insulation film and manufacturing method thereof An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation film 10 is provided with rows of... |
| US-6,894,366 |
Bipolar junction transistor with a counterdoped collector region An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the... |
| US-6,894,318 |
Diode having a double implanted guard ring The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the... |
| US-6,894,308 |
IC with comparator receiving expected and mask data from pads Test circuits located on semiconductor die enable a tester to scan test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to... |
| US-6,893,924 |
Dual metal-alloy nitride gate electrodes An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190.... |
| US-6,892,380 |
Method for software pipelining of irregular conditional control loops A method for software pipelining of irregular conditional control loops including pre-processing the loops so they can be safely software pipelined. The... |
| US-6,892,266 |
Multicore DSP device having coupled subsystem memory buses for global DMA
access A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment,... |
| US-6,892,253 |
Maintaining remote queue using two counters in transfer controller with hub
and ports The data transfer apparatus and method employs two queue counters to maintain the status of a first-in-first-out buffer memory. A master count (251) indicates... |
| US-6,892,170 |
Method and apparatus for modeling mass storage disk drive motors The present invention provides an improved model and methodology for simulating motor performance which allow increased control accuracy at the higher currents,... |
| US-6,892,148 |
Circuit and method for measurement of battery capacity fade The remaining run-time (t_rem) of a battery is determined independently of the condition of the battery and the amount of load on the battery by obtaining the... |
| US-6,892,103 |
Digital tone control with linear step coefficients Digital audio tone control implemented using Shelving filters for the digital audio treble tone control exhibits artifacts (noise, distortion, etc.) as the tone... |
| US-6,891,968 |
Method to upscale single-pixel wide text without loss of image sharpness A method to upscale single pixel wide text associated with flat panel display applications has a reduced cross-sectional area in two dimensions as compared to... |
| US-6,891,882 |
Receiver algorithm for the length 4 CFC Decoding CFC codewords in the form of sums of QPSK-modulated spread symbols in a spread spectrum communications systems using comma-free codes with elements made... |
| US-6,891,657 |
Damped control of a micromechanical device Device and method for a damping function to reduce undesirable mechanical transient responses to control signals. In one aspect of the present invention, the... |
| US-6,891,541 |
Graphing calculator with manual line drawing A graphing calculator (10) having manual line drawing capability. The calculator (10) is programmed to receive data representing the begin point and end point of... |
| US-6,891,486 |
Calibrating capacitor mismatch in a pipeline ADC An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to... |
| US-6,890,836 |
Scribe street width reduction by deep trench and shallow saw cut In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer... |
| US-6,890,826 |
Method of making bipolar transistor with integrated base contact and field
plate A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a... |
| US-6,889,362 |
User interface for graphical specification of functions A graphing calculator having a user interface that allows the user to easily specify a mathematical function. The user interface allows the user to specify a... |
| US-6,889,330 |
Dynamic hardware configuration for energy management systems using task
attributes A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management... |
| US-6,889,320 |
Microprocessor with an instruction immediately next to a branch instruction
for adding a constant to a program... A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution... |
| US-6,889,311 |
Pipeline stage single cycle sliding alignment correction of memory read
data with integrated data reordering... Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively... |
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