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Patent # Description
US-6,870,426 Output stage, amplifier and associated method for limiting an amplifier output
A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer...
US-6,870,406 Output driver circuit
An output driver circuit includes an input stage to which an input voltage is applied, and an output stage to which an output voltage is applied, input stage and...
US-6,870,389 Differential circuit with current overshoot suppression
A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair...
US-6,870,382 System and method for evaluating the planarity and parallelism of an array of probe tips
A system includes a support member and a computer system. The support member holds and retains a probe card, which has an array of probe tips extending...
US-6,870,375 System and method for measuring a capacitance associated with an integrated circuit
A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated...
US-6,870,345 Servo loop PID compensator with embedded rate limit
This invention describes a reconfigured form of the PID compensator such that the rate of change of the position error is inherently limited without affecting...
US-6,870,242 Method for manufacturing and structure of semiconductor device with polysilicon definition structure
A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation...
US-6,869,875 Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process
An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In...
US-6,869,862 Method for improving a physical property defect value of a gate dielectric
The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated...
US-6,869,851 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without...
A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is...
US-6,869,840 Compensated-well electrostatic discharge protection devices
Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor...
US-6,869,831 Adhesion by plasma conditioning of semiconductor chip surfaces
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-6,869,011 Apparatus and method for controlling an electrical switch array
An electrical switching apparatus configured for low power operation includes: (a) a plurality of switching devices arranged in a switching array permitting...
US-6,868,376 Debug bi-phase export and data recovery
An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an...
US-6,868,298 Method and apparatus for bottleneck feed factor based scheduling
A method and system for scheduling lots for semiconductor manufacturing. The method and system comprising: determining a goal weighing factor (502); calculating...
US-6,868,087 Request queue manager in transfer controller with hub and ports
A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as...
US-6,867,997 Series feram cell array
Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline....
US-6,867,777 Tracing and storing points of interest on a graphing calculator
A graphing calculator (10) having an X=Editor with inequalities. The calculator (10) is programmed to provide an X=Editor which displays one or more "X=" to...
US-6,867,722 H-bridge common-mode noise reduction circuit
A common-mode noise reduction circuit (20) adapted to receive a DIN input (-1, 0, +1), such as from a sigma-delta modulator (12), and provide alternating outputs...
US-6,867,653 Apparatus and method for converting a fully-differential class-AB input signal to a rail-to-rail single ended...
An apparatus for converting a fully-differential input signal to an output signal which varies between two rail limits and includes: (a) a first buffer receiving...
US-6,867,652 Fast-response current limiting
An amplifier (10") has a first amplifier stage (14) for producing a control current (I.sub.X) in response to an input voltage. A second amplifier stage (16) has...
US-6,867,503 Controlling interdiffusion rates in metal interconnection structures
A metal interconnection structure for semiconductor chips has a metal interface layer (105), preferably nickel, deposited over the metal of the chip contact pad...
US-6,867,447 Ferroelectric memory cell and methods for fabricating the same
Semiconductor devices and ferroelectric memory cells therefor are provided, where the cells include a ferroelectric capacitor with one or more corners, as well...
US-6,867,100 System for high-precision double-diffused MOS transistors
The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's...
US-6,866,974 Semiconductor process using delay-compensated exposure
A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and...
US-6,865,694 CPU-based system and method for testing embedded memory
A CPU-based system 10 and method for testing embedded memory. The technique employs the on-chip CPU 20 itself to test the embedded memory 24. An assembly code...
US-6,865,504 Apparatus and method for a reconfigurable pod interface for use with an emulator unit
A reconfigurable cable/pod unit replaces the cable/pod unit coupling an emulation unit and a target processor. The reconfigurable cable/pod unit includes the...
US-6,865,222 Method and apparatus for testing a serial transmitter circuit
An integrated circuit (12) contains a serializing transmitter, including a phase locked loop (31) that supplies seven clocks (41) with different phases to a...
US-6,864,818 Programmable bandpass analog to digital converter based on error feedback architecture
A delta sigma modulator based analog to digital converter is presented, having a first quantizer and a digital error feedback system comprising a second...
US-6,864,751 Transimpedance amplifier with adjustable output amplitude and wide input dynamic-range
A transimpedance amplifier circuit comprising transistors, a constant current source, a load resistor, and the feedback resistor with a shunt circuitry...
US-6,864,738 CMOS voltage booster circuits
This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage...
US-6,864,708 Suppressing the leakage current in an integrated circuit
A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the...
US-6,864,702 System for oxide stress testing
The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present...
US-6,864,108 Measurement of wafer temperature in semiconductor processing chambers
A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10)....
US-6,863,401 Illumination system
The addition of DMD illumination modulator(s) 702 in series with projection SLM(s) 706/709 to produce high-performance projection displays with improved optical...
US-6,862,658 Retrieving streams of data from rotating storage medium while balancing various requirements
Parameters characterizing physical operation of a rotating structure (disk drive) are determined by sending appropriate commands and examining the response. The...
US-6,862,640 Arbitration in local system for access to memory in a distant subsystem
A multiprocessor system includes a plurality of data processors. Each data processor includes: a data processing core; a memory forming a local portion of a...
US-6,862,495 In-situ randomization and recording of wafer processing order at process tools
Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing...
US-6,862,398 System for directed molecular interaction in surface plasmon resonance analysis
Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface...
US-6,862,333 CMD and CMD-carrying CCD device
This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such...
US-6,862,275 Cell selection with STTD and SSDT
A method of operating a communication circuit comprises the steps of receiving a plurality of signals (508-509, 514-516) from a plurality of remote transmitters...
US-6,861,901 Voltage follower circuit
A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect...
US-6,861,832 Threshold voltage adjustment for MOS devices
The Vt of an MOS transistor is lowered in response to its load current. In a LDO (low dropout) regulator, lowering the Vt of the pass transistor with load...
US-6,861,826 Timing circuit for synchronous DC/DC control to reduce synchronous rectifier body diode conduction
A control device and method for synchronizing activation and deactivation of a high-side switch (102) and a low-side switch (104) in a converter including an...
US-6,861,721 Barrier region and method for wafer scale package (WCSP) devices
A barrier region provided in the active surface of a wafer-level chip scale package device or chip (WCSP device or chip) to substantially reduce the amount of...
US-6,861,678 Double diffused vertical JFET
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-6,861,608 Process and system to package residual quantities of wafer level packages
Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include...
US-6,861,348 Pre-pattern surface modification of low-k dielectrics
A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction...
US-6,861,303 JFET structure for integrated circuit and fabrication method
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in...
US-6,861,292 Composite lid for land grid array (LGA) flip-chip package assembly
A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back...
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