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A socket for receiving a line of contact pins is formed of modules connected together. The modules have three, four or five pin receiving openings and are joined...
TIR prism arrangement and optics for providing an undistorted illumination
A lens system for providing undistorted illumination image onto a light receiving surface such as a DMD.TM. (digital micromirror device) light modulator with a...
Turbo decoder stopping based on mean and variance of extrinsics
An adaptive stopping criterion improvement for an iterative decoder, in which iteration is halted by observing a signal-to-noise ratio generated from the mean...
Method to increase head voltage swing and to reduce the rise time of write
A voltage-mode boosting write driver circuit (40) having a pair of voltage boosting PMOS transistor sets (44, 46) coupled to a high current H-switch (42). One...
Neutral density color filters
The present application describes embodiments of a neutral density color wheel filter. According to one embodiment, a neutral density color wheel (100) includes...
Differential pipelined analog to digital converter with successive
approximation register subconverter stages
Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are...
Package with environmental control material carrier
A drop-in environmental control material carrier assembly 55, which improves the performance and lowers the cost of semiconductor packages. The disclosed...
Integrated thermal difference sensor for power dissipating device
A Seebeck effect thermal sensor is formed in an integrated fashion with a power-dissipating device such as a power MOSFET. The integrated device generates a...
Transistor with improved safe operating area
Segmented transistor devices are provided, wherein contiguous individual transistor segments extend along corresponding segment axes, in which two or more of the...
Method for improving ash rate uniformity in photoresist ashing process
A method for improving the edge-to-center photoresist ash rate uniformity in lower temperature (typically, but not limited to <100.degree. C.) processing of...
Compliant wirebond pedestal
A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906)....
Link instruction register providing test control signals to core wrappers
A separate link instruction register is connected in series in a test data and instruction data scan path on an IC. Instruction data shifted into the register...
Booth encoding circuit for a multiplier of a multiply-accumulate module
A Booth encoding circuit includes a plurality of cells (202a-202d), in which at least one of the cells (202c) includes a plurality of inputs. The cell also...
Measuring constraint parameters at different combinations of circuit
The value of a constraint parameter for a given combination of circuit parameters is estimated based on any prior computed values for other combinations of...
Method and apparatus for tuning digital hearing aids
A method for generating digital filters for tuning a hearing aid to enhance hearing ability. Data is provided, for a range for a target response curve ...
Integrated circuit with programmable fuse array
An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the...
Method of context based adaptive binary arithmetic decoding with two part
This invention is method of decoding a context based adaptive binary arithmetic encoded bit stream. The invention determines a maximum number of iterations for...
Technique for generating carrier frequencies with fast hopping capability
A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique...
Reducing electro magnetic interference (EMI) in integrated circuits
operating on both analog and digital signals
EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal...
Semiconductor device and its manufacturing method
Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor...
Masking layer in substrate cavity
A package that resists creation of particles in a package cavity. A package according to one embodiment of the present invention contains a mechanical device...
Use of amorphous aluminum oxide on a capacitor sidewall for use as a
The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier...
Method for improving silicon-on-insulator (SOI) film uniformity on a
A method for improving the thickness uniformity of a silicon-on-insulator (SOI) film on a semiconductor wafer. The preferred embodiments disclose using a...
Eliminating substrate noise by an electrically isolated high-voltage I/O
On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite...
Semiconductor package insulation film and manufacturing method thereof
An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation film 10 is provided with rows of...
Subexpression selection of expression represented in contiguous tokenized
An algorithm and handheld device adapted to select a subexpression of a mathematical expression. An expression string of the handheld device is selected, and the...
Spread spectrum time tracking
Time tracking units with decision statistics mitigating or correcting for influences from nearby interfering paths. Interference mitigation is accomplished by...
Digital still camera system and method
A digital still camera with video playback capabilities including a hybrid buffer for variable length frame decoding, the hybrid having two buffers with each...
Shared data buffer in FeRAM utilizing word line direction segmentation
A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture....
System and method for electrostatic discharge protection using lateral PNP
or PMOS or both for substrate biasing
The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10)...
Use of configurable capacitors to tune a self biased phase locked loop
A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency...
Integrated circuit testing device and a method of use therefor
The present invention provides an integrated circuit testing device 200 and a method of using the same. In one particular embodiment, the integrated circuit...
Semiconductor package with metal foil attachment film
A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by...
Semiconductor packages for enhanced number of terminals, speed and power
An integrated circuit device package with a first part (101) having a cavity (104) to mount the chip (105), further I/O terminals (102) on the top surface and...
MOS transistors having higher drain current without reduced breakdown
A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable...
Asymmetrical devices for short gate length performance with disposable
An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V.sub.T net dopant adjacent...
Reduced size plate layer improves misalignments for CUB DRAM
In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in...
PZT (111) texture through Ir texture improvement
The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom...
Process flow for dual damescene interconnect structures
A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k...
Method of forming an integrated circuit thin film resistor
A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias...
Method for preventing polysilicon mushrooming during selective epitaxial
Methods are presented, in which an oxide protection layer is provided on a gate structure for protection against poly mushrooming during selective epitaxial...
Vertical mold die press machine
A die mold machine for molding a plurality of semiconductor assemblies on multiple substrate/leadframes includes a plurality of die mold layers stacked...
Selective trim and wafer testing of integrated circuits
A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the...
Method for aligning substrates in a tray
A substrate 110 that is not lying flat on its substrate tray 100 can present significant process problems when a vacuum pickup attempts to pick up the substrate...
Control circuit for synchronous rectifiers in DC/DC converters to reduce
body diode conduction losses
A controller for a switching power supply having first and second synchronous rectifiers that minimizes the reverse recovery time and body diode conduction...
Digital micromirror device having mirror-attached spring tips
A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of three operating layers 12, 13, 14. An addressing layer 12 is...
System for directed molecular interaction in surface plasmon resonance
Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface...
Invalid shape detector (ISD)
A method to detect invalid polygons that are inputted by users using a graphical user-interface is presented. The method selects pairs of lines that are used to...
Output stage, amplifier and associated method for limiting an amplifier
A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer...
Output driver circuit
An output driver circuit includes an input stage to which an input voltage is applied, and an output stage to which an output voltage is applied, input stage and...