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Method for data packet acquisition using split preamble
A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a...
Range based detection of memory access
Memory accesses in a data processing device (14) can be monitored by selecting, from among a plurality of available memory relationships (37, 82), a memory...
Immediate grant bus arbiter for bus system
The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect...
Transpose FIR filter architecture
A novel Finite Impulse Response ("FIR") filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input...
Power switching circuit with controlled reverse leakage
A power switching circuit including an MOS power switching transistor (P1) is disclosed. The power switching transistor (P1) has a body node that is selectably...
Low power mode detection circuit for a DC/DC converter
A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a...
Method of fabricating a molded package for micromechanical devices
A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process...
Complementary transistors having respective gates formed from a metal and a
A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the...
Efficient ESD protection with application for low capacitance I/O pads
A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a...
Vertical bipolar transistor formed using CMOS processes
A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect...
Adaptive illumination modulator
An image display system includes a light source capable of generating an illumination light beam along an illumination path. The system also includes a modulator...
Wirefilm bonding for electronic component interconnection
A system (30) is provided for interconnecting a first component (10) having multiple first bonding sites (16) and a second component (12) having multiple second...
Active removal of aliasing frequencies in a decimating structure by
changing a decimation ratio in time and space
When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss...
Using phase interpolator information to detect a loss of lock condition
during recovery of a clock signal from...
A loss of lock condition of a clock signal (25) recovered from a received data stream can be detected by examining conventionally available information (25, 26)...
Timing recovery device and method for telecommunications systems
A timing recovery device for CAP/QAM modems includes an equalizer filter designed to monitor the movement of the filter coefficients within a memory buffer and...
Wireless code division multiple access communications system with channel
estimation using fingers with...
A wireless communication network (10). The network comprises a wireless receiver (14). The receiver comprises at least one antenna (AT.sub.14) for receiving a...
Reference voltage generator for ferroelectric memory
Apparatus and methods are provided for providing reference voltages during read operations in ferroelectric memories, in which a bitline of a reference array...
Ferroelectric memory with wide operating voltage and multi-bit storage per
Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states...
Apparatus and method for providing a read signal for an information
An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information;...
Phase tolerant servo gray code detector
Methods and apparatus are disclosed for detecting PR4 equalized Gray codes, providing phase tolerant Gray codes and detection thereof. A Gray code detector is...
Color splitting apparatus and method with unequal glass path lengths
A three element prism system and method for splitting/combining three different colors of light arranged such that the size of a selected one of the color prism,...
Digital micromirror device having mirror-attached spring tips
A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of three operating layers 12, 13, 14. An addressing layer 12 is...
Method for decoding reversible variable length code using leading-zeros
variable length decoding techniques
A method for decoding a bitstream of reversible variable length codewords parses the bitstream to extract a next reversible variable length codeword, transcodes...
Preamplifier system with selectable input impedance
Systems and methods are provided for selecting an input impedance of a preamplifier device. Multiple feedback paths are provided to an amplifier device of the...
Current source/sink with high output impedance using bipolar transistors
A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by...
Versatile system for high resolution device calibration
The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the...
System and method for measuring a capacitance of a conductor
A method for measuring a capacitance of a device under test is provided that includes selectively charging and discharging a first conductor with a first set of...
A regulator circuit capable of reducing an increase in an output voltage during a sudden drop in a load current without increasing the power consumption during a...
Detection circuit having an adaptive threshold
A voltage detection circuit utilizes a comparator to compare first and second input voltages to generate a control signal when the difference between the first...
Method for fabricating a lid for a wafer level packaged optical MEMS device
A method of individually packaging a multiplicity of devices, such as a spatial light modulator, before the multiplicity of devices formed on a substrate wafer...
Reduce 1/f noise in NPN transistors without degrading the properties of PNP
transistors in integrated circuit...
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively...
Process to reduce gate edge drain leakage in semiconductor devices
The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted...
Vibration-assisted method for underfilling flip-chip electronic devices
A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less...
Method and apparatus for calibration of an electronic device
A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high...
Apparatus and method for simultaneously displaying a number along with its
number of significant figures
A computing device (40) comprises an electrical circuit and a software application. A display screen (138) and an input device (140) are electrically coupled to...
Provisioning of subscriber services
A system for provisioning of enhanced telephone services by the subscriber is provided for a base telephone account. The system allows enhanced services that are...
Reducing leakage current in circuits implemented using CMOS transistors
Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the...
High-speed low-capacitive load common mode feedback
A variable gain amplifier to output a differential output signal includes an input circuit to input a differential input signal, a buffer circuit to buffer the...
Gated scan output flip-flop
A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage...
Integrated circuit leadframes patterned for measuring the accurate
amplitude of changing currents
A metallic leadframe for use with a semiconductor chip intended for operation in a changing magnetic field comprises a chip mount pad having at least one slit...
DC-DC converter and DC-DC converter drive circuit
The objective of this invention is to provide a DC-DC converter characterized by the fact that by correcting the loop gain corresponding to the switching of the...
High temperature interface layer growth for high-k gate dielectric
The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture...
Fabrication of abrupt ultra-shallow junctions
One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity...
Digital PLL with gear shift
A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, .alpha.. During frequency/phase acquisition, a larger loop gain constant,...
Integrated refrigeration control
An integrated refrigeration control (IRC) module is disclosed which combines both thermal and electrical protection to the main components of a refrigerator and...
Fault management and recovery based on task-ID
In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a processor and a memory. A plurality...
Worst case performance modeling of analog circuits
A computer system (30) and method of operating the same to model worst case performances of an analog circuit is disclosed. The computer system (30) includes...
Master-slave latch with transparent mode
A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the...
Low leakage single-step latch circuit
This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch...
Multi-phase and multi-module power system with a current share bus
A pulse width modulator (305) for driving a load in a multi-phased power system having circuitry (270) responsive to channel signals for providing an average...