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Patent # Description
US-6,876,750 Method and apparatus for tuning digital hearing aids
A method for generating digital filters for tuning a hearing aid to enhance hearing ability. Data is provided, for a range for a target response curve ...
US-6,876,594 Integrated circuit with programmable fuse array
An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the...
US-6,876,317 Method of context based adaptive binary arithmetic decoding with two part symbol decoding
This invention is method of decoding a context based adaptive binary arithmetic encoded bit stream. The invention determines a maximum number of iterations for...
US-6,876,262 Technique for generating carrier frequencies with fast hopping capability
A technique for generating carrier frequencies with fast hopping capability associated with multiband systems for ultra wideband applications. The technique...
US-6,876,223 Reducing electro magnetic interference (EMI) in integrated circuits operating on both analog and digital signals
EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal...
US-6,876,077 Semiconductor device and its manufacturing method
Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor...
US-6,876,071 Masking layer in substrate cavity
A package that resists creation of particles in a package cavity. A package according to one embodiment of the present invention contains a mechanical device...
US-6,876,021 Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier
The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier...
US-6,875,656 Method for improving silicon-on-insulator (SOI) film uniformity on a semiconductor wafer
A method for improving the thickness uniformity of a silicon-on-insulator (SOI) film on a semiconductor wafer. The preferred embodiments disclose using a...
US-6,875,650 Eliminating substrate noise by an electrically isolated high-voltage I/O transistor
On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite...
US-6,875,637 Semiconductor package insulation film and manufacturing method thereof
An insulation film for providing an insulation substrate carrying a semiconductor chip of a semiconductor package. Insulation film 10 is provided with rows of...
US-6,874,005 Subexpression selection of expression represented in contiguous tokenized polish representation
An algorithm and handheld device adapted to select a subexpression of a mathematical expression. An expression string of the handheld device is selected, and the...
US-6,873,667 Spread spectrum time tracking
Time tracking units with decision statistics mitigating or correcting for influences from nearby interfering paths. Interference mitigation is accomplished by...
US-6,873,658 Digital still camera system and method
A digital still camera with video playback capabilities including a hybrid buffer for variable length frame decoding, the hybrid having two buffers with each...
US-6,873,536 Shared data buffer in FeRAM utilizing word line direction segmentation
A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture....
US-6,873,506 System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing
The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10)...
US-6,873,214 Use of configurable capacitors to tune a self biased phase locked loop
A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency...
US-6,873,146 Integrated circuit testing device and a method of use therefor
The present invention provides an integrated circuit testing device 200 and a method of using the same. In one particular embodiment, the integrated circuit...
US-6,873,059 Semiconductor package with metal foil attachment film
A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by...
US-6,873,040 Semiconductor packages for enhanced number of terminals, speed and power performance
An integrated circuit device package with a first part (101) having a cavity (104) to mount the chip (105), further I/O terminals (102) on the top surface and...
US-6,873,021 MOS transistors having higher drain current without reduced breakdown voltage
A drain-extended MOS transistor in a semiconductor wafer (300) of a first conductivity type comprises a first well (315) of the first conductivity type, operable...
US-6,873,008 Asymmetrical devices for short gate length performance with disposable sidewall
An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V.sub.T net dopant adjacent...
US-6,873,001 Reduced size plate layer improves misalignments for CUB DRAM
In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in...
US-6,872,669 PZT (111) texture through Ir texture improvement
The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom...
US-6,872,665 Process flow for dual damescene interconnect structures
A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k...
US-6,872,655 Method of forming an integrated circuit thin film resistor
A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias...
US-6,872,610 Method for preventing polysilicon mushrooming during selective epitaxial processing
Methods are presented, in which an oxide protection layer is provided on a gate structure for protection against poly mushrooming during selective epitaxial...
US-6,872,593 Vertical mold die press machine
A die mold machine for molding a plurality of semiconductor assemblies on multiple substrate/leadframes includes a plurality of die mold layers stacked...
US-6,872,582 Selective trim and wafer testing of integrated circuits
A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the...
US-6,871,394 Method for aligning substrates in a tray
A substrate 110 that is not lying flat on its substrate tray 100 can present significant process problems when a vacuum pickup attempts to pick up the substrate...
US-6,870,747 Control circuit for synchronous rectifiers in DC/DC converters to reduce body diode conduction losses
A controller for a switching power supply having first and second synchronous rectifiers that minimizes the reverse recovery time and body diode conduction...
US-6,870,660 Digital micromirror device having mirror-attached spring tips
A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of three operating layers 12, 13, 14. An addressing layer 12 is...
US-6,870,627 System for directed molecular interaction in surface plasmon resonance analysis
Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface...
US-6,870,533 Invalid shape detector (ISD)
A method to detect invalid polygons that are inputted by users using a graphical user-interface is presented. The method selects pairs of lines that are used to...
US-6,870,426 Output stage, amplifier and associated method for limiting an amplifier output
A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer...
US-6,870,406 Output driver circuit
An output driver circuit includes an input stage to which an input voltage is applied, and an output stage to which an output voltage is applied, input stage and...
US-6,870,389 Differential circuit with current overshoot suppression
A differential driver circuit that suppresses current overshoot and allows current switching to proceed at near the maximum speed includes: a differential pair...
US-6,870,382 System and method for evaluating the planarity and parallelism of an array of probe tips
A system includes a support member and a computer system. The support member holds and retains a probe card, which has an array of probe tips extending...
US-6,870,375 System and method for measuring a capacitance associated with an integrated circuit
A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated...
US-6,870,345 Servo loop PID compensator with embedded rate limit
This invention describes a reconfigured form of the PID compensator such that the rate of change of the position error is inherently limited without affecting...
US-6,870,242 Method for manufacturing and structure of semiconductor device with polysilicon definition structure
A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation...
US-6,869,875 Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process
An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In...
US-6,869,862 Method for improving a physical property defect value of a gate dielectric
The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated...
US-6,869,851 Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without...
A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is...
US-6,869,840 Compensated-well electrostatic discharge protection devices
Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor...
US-6,869,831 Adhesion by plasma conditioning of semiconductor chip surfaces
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-6,869,011 Apparatus and method for controlling an electrical switch array
An electrical switching apparatus configured for low power operation includes: (a) a plurality of switching devices arranged in a switching array permitting...
US-6,868,376 Debug bi-phase export and data recovery
An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an...
US-6,868,298 Method and apparatus for bottleneck feed factor based scheduling
A method and system for scheduling lots for semiconductor manufacturing. The method and system comprising: determining a goal weighing factor (502); calculating...
US-6,868,087 Request queue manager in transfer controller with hub and ports
A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as...
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