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| Patent # | Description |
|---|---|
| US-7,132,365 |
Treatment of silicon prior to nickel silicide formation A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may... |
| US-7,132,359 |
Tolerance bondwire inductors for analog circuitry Disclosed are wirebonding methods wherein bondwires are positioned using dynamically determined variations in die placement. Preferred methods of the invention... |
| US-7,132,340 |
Application of post-pattern resist trim for reducing pocket-shadowing in
SRAMs Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate... |
| US-7,132,314 |
System and method for forming one or more integrated circuit packages
using a flexible leadframe structure In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars... |
| US-7,131,762 |
Color rendering of illumination light in display systems A method and apparatus for compensating for deficiency in the illumination light from a light source is provided, where the spectrum in the visible range of... |
| US-7,131,114 |
Debugger breakpoint management in a multicore DSP device having shared
program memory A processing system comprises a digital signal processor (DSP) device and a host system on which the DSP device is implemented. The DSP device comprises a shared... |
| US-7,131,089 |
Computer program for programming an integrated circuit speed capability
indicator A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path... |
| US-7,131,044 |
Means scanning scan path parts sequentially and capturing response
simultaneously Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan... |
| US-7,130,984 |
First-in first-out memory system with shift register fill indication An electronic device (10). The device comprises a memory structure (12) comprising an integer M of word storage locations. The device further comprises a write... |
| US-7,130,749 |
Wavelet analysis of signals to determine characteristics of anomalies in a
wire In one embodiment, a method for wavelet analysis of one or more signals to determine one or more characteristics of one or more anomalies in a wire includes... |
| US-7,130,415 |
Line Driver apparatus A line driver apparatus includes a peak detector operable to receive a data signal and output a first logic signal when the data signal is below a threshold... |
| US-7,130,345 |
Configurable equalization apparatus for multicarrier communications A number of basic equalization and demodulation structures have been shown to be appropriate for DMT systems depending on the channel, noise, and system... |
| US-7,130,335 |
Multi-line ADSL modem A multi-line ADSL modem (12) and network (10) whereby the multi-line ADSL modem (12) has connections to several ADSL modems (14) at a central office (CO) (16)... |
| US-7,130,182 |
Stacked capacitor and method for fabricating same The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a... |
| US-7,130,169 |
Short circuit protection for a power isolation device and associated diode Short circuit protection is provided for an isolation component that has a parasitic diode as an inherent part of its construction. The isolation component may... |
| US-7,130,105 |
Method and apparatus for controlling the positioning of an optical
dithering element According to one embodiment, a method for controlling positioning of an optical dithering element includes repeatedly driving the optical dithering element... |
| US-7,130,073 |
Efficient storage and rendering of patterns in a printer Patterns are processed minimizing resources such as memory and/or processing power. According to one aspect, when a pattern object is received with the same... |
| US-7,129,875 |
Tracking reference system for analog-to-digital converter systems An analog-to-digital (A/D) converter system is provided that compensates for operating variations associated with one or more passive components of the A/D... |
| US-7,129,862 |
Decoding bit streams encoded according to variable length codes A decoding approaching suitable for architectures such as Very Long Instruction Word (VLIW), in which throughput performance would be reduced in case if large... |
| US-7,129,766 |
CMOS analog switch A CMOS analog switch is provided that can handle negative input polarity. The semiconductor substrate wherein the analog switch is formed has a substrate area of... |
| US-7,129,752 |
High-speed lever shifter with AC feed-forward An improved level shifter circuit with AC feed-forward is disclosed. The integrated circuit device includes a first circuit part biased from a lower voltage... |
| US-7,129,740 |
Low noise output buffer The strength of the output buffer is changed gradually when there is a transition in the output (or input) value. Due to the gradual change, switching noise is... |
| US-7,129,735 |
Method for test data-driven statistical detection of outlier semiconductor
devices A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die... |
| US-7,129,734 |
Method for testing analog and mixed-signal circuits using functionally
related excitations and functionally... A method for testing a circuit includes determining at least one performance characteristic of the circuit based on a functional relationship between excitation... |
| US-7,129,696 |
Method for capacitance measurement in silicon A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a plurality of selectable devices under test (DUT)... |
| US-7,129,652 |
System and method for driving a plurality of loads A system for controlling a plurality of load devices includes a high-side system operative to source current relative to at least two associated outputs. A... |
| US-7,129,582 |
Reducing the migration of grain boundaries A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate... |
| US-7,129,162 |
Dual cap layer in damascene interconnection processes Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an... |
| US-7,129,127 |
Integration scheme to improve NMOS with poly cap while mitigating PMOS
degradation A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active... |
| US-7,127,794 |
Auto-boating process According to one embodiment of the invention, a method for auto-boating includes supporting a tape substrate having first and second end portions on a boat,... |
| US-7,127,734 |
System and methods for home network communications The present invention provides the ability to use existing cable TV wires for home networking. |
| US-7,127,639 |
Distinguishing between two classes of trace information A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time... |
| US-7,127,604 |
Changing a codec or MAC size without affecting the encryption key in
PacketCable communication A technique is described to change the codec or MAC (message authentication code) size in a packet security unit for PacketCable communications during realtime... |
| US-7,127,387 |
Multi-port trace data handling A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port,... |
| US-7,127,359 |
Real-time mathematical model for wafer spin defect detection and for
misalignment analyses According to various embodiments, there is a method of inspecting semiconductor wafers comprising comparing a value for each wafer in a lot of wafers to a... |
| US-7,127,020 |
Frequency synthesis loop having controlled loop gain A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward... |
| US-7,126,889 |
Tracking error detector A circuit to improve the SN characteristic of a tracking error signal. This tracking error detection circuit is formed as a push-pull system utilizing a quadrant... |
| US-7,126,744 |
Stabilization of closed loop operation of a torsional hinged device Apparatus and methods for removing jitter and stabilizing the feed back system of a torsional hinged device with minimal changes to the system. The stabilization... |
| US-7,126,711 |
Voice/facsimile/modem call discrimination method for voice over packet
networks A method of discriminating voice, data, and facsimile calls communicated through a voice-over-packet network. The gateway is provided with software which can... |
| US-7,126,523 |
Reducing errors and power consumption in a multi-stage analog to digital
converter (ADC) using amplifier... An amplifier sharing technique in an analog to digital converter (ADC) in which a cascaded combination of a pre-amplifier and main amplifier is used to provide... |
| US-7,126,415 |
Switched-capacitor circuits with reduced finite-gain effect Operational amplifier circuits (20, 30) including error capacitors (C.sub.3, C13) for storing finite gain effect error voltages for correction of output voltages... |
| US-7,126,217 |
Arrangement in semiconductor packages for inhibiting adhesion of lid to
substrate while providing compression... In a semiconductor flip-chip package having a semiconductor die 104 as part of a substrate assembly, a lid 110 (or lid assembly) and substrate 102 are supported... |
| US-7,125,789 |
Composite metal column for mounting semiconductor device An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external... |
| US-7,124,341 |
Integrated circuit having electrically isolatable test circuitry Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test.... |
| US-7,123,772 |
Image compression by differences within a strip A method of image/video compression by analysis of variability of block DCT coefficients in a strip of (macro)blocks to decide on treatment of the blocks in the... |
| US-7,123,671 |
Automatic gain control method for digital subscriber line modems The present invention provides automatic gain control (AGC) for a wide variety of conditions encountered in DSL scenarios. In particular, the proposed AGC... |
| US-7,123,666 |
Gaussian minimum shift key transmitter with feedforward phase compensation A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward... |
| US-7,123,665 |
Method and apparatus for measuring phase error of a modulated signal A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward... |
| US-7,123,178 |
Digital encoder and digital-to-analog converter using same A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes... |
| US-7,123,085 |
Rail-to-rail charge pump with replica circuitry The charge pump circuit includes: a charge pump output branch having a first transistor and a second transistor coupled in series; an output branch replica... |
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