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| Patent # | Description |
|---|---|
| US-7,067,441 |
Damage-free resist removal process for ultra-low-k processing A process for removing resist (114) from a CDO dielectric material (110) that uses a non-damaging plasma in a reducing atmosphere under high power and using a... |
| US-7,067,435 |
Method for etch-stop layer etching during damascene dielectric etching
with low polymerization The present invention provides a method for etching a substrate 100. The method includes conducting a first etch through a dielectric layer 130 located over an... |
| US-7,067,434 |
Hydrogen free integration of high-k gate dielectrics The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this... |
| US-7,067,015 |
Modified clean chemistry and megasonic nozzle for removing backside CMP
slurries A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment... |
| US-7,066,608 |
Lamp reflector assembly A lamp assembly having a reflector (102) holding a lamp element, or burner (104). The reflector (102) typically is an ellipse, with the burner arc positioned at... |
| US-7,066,605 |
Color recapture for display systems A sequential color display system using a white light source to create a full color image projected onto an image plane. A dynamic filter, typically a series of... |
| US-7,065,699 |
Using quadrant shifting to facilitate binary arithmetic with two's
complement operands Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an... |
| US-7,065,692 |
IC with external register present lead connected to instruction register An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test... |
| US-7,065,669 |
System and method for providing a write strobe signal to a receiving
element before both an address and data signal A method and apparatus is provided for that includes an improved special function register (SFR) access scheme by using a clock tree distribution process. In... |
| US-7,065,498 |
Supply of digital audio and video products A server for a merchant computer system, the server comprising: a file store for storing a range of audio/video products in respective product files; a dialogue... |
| US-7,065,380 |
Software partition of MIDI synthesizer for HOST/DSP (OMAP) architecture A system and method implements optimal task partitioning between a general purpose processor (GPP) and a digital signal processor (DSP) to replace a fixed... |
| US-7,065,172 |
Precision jitter-free frequency synthesis An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a... |
| US-7,065,166 |
Wireless receiver and method for determining a representation of noise
level of a signal A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain... |
| US-7,065,147 |
System and method of data communication using turbo trellis coded
modulation combined with constellation... A technique that combines a turbo trellis coded modulation (TTCM) coding scheme with constellation shaping and precoding schemes to implement a binary coded... |
| US-7,064,694 |
Multi-cycle, multi-slope analog to digital converter A multi-cycle, multi-slope analog to digital converter overlaps charge and discharge periods to reduce latency to the end of the measurement following a sampling... |
| US-7,064,682 |
Relaxation oscillator based keypad decoder The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC... |
| US-7,064,607 |
Bias system and method A bias device that modifies the bias of a device based on an input signal to the device. The device may have a fixed bias, and the bias device can be connected... |
| US-7,064,593 |
Bus-hold circuit A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current `I.sub.off` specification without incorporating a diode in pull-up... |
| US-7,064,587 |
Output Buffer A low-noise output buffer for a digital signal is based on an analog amplifier having bandwidth greater than the switching rate of the digital logic signal. A... |
| US-7,064,399 |
Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer... |
| US-7,064,043 |
Wafer bonded MOS decoupling capacitor A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the... |
| US-7,064,039 |
Method to produce localized halo for MOS transistor Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a... |
| US-7,064,008 |
Semiconductor leadframes plated with thick nickel, minimum palladium, and
pure tin A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of pure... |
| US-7,062,762 |
Partitioning symmetric nodes efficiently in a split register file
architecture The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of... |
| US-7,062,680 |
Expert system for protocols analysis An expert system that provides an analysis of protocol exchanges and protocol relationships across multiple data units, such as packets, of a network and within... |
| US-7,062,635 |
Processor system and method providing data to selected sub-units in a
processor functional unit A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an... |
| US-7,062,526 |
Microprocessor with rounding multiply instructions A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is... |
| US-7,062,433 |
Method of speech recognition with compensation for both channel distortion
and background noise A method of speech recognition with compensation is provided by modifying HMM models trained on clean speech with cepstral mean normalization. For all speech... |
| US-7,062,430 |
Designing boundary filters for a biorthogonal filter bank A signal processing device includes a biorthogonal filter bank that processes a finite length signal including a left boundary and a right boundary. The... |
| US-7,062,304 |
Task based adaptative profiling and debugging A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management... |
| US-7,062,244 |
Speed-up mode implementation for direct conversion receiver A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up... |
| US-7,062,037 |
Generic line impedance matching circuit using decomposed configurable
transfer functions A technique for implementing impedance matching circuits 100 that use the transfer functions of each line impedance model. This technique allows implementation... |
| US-7,062,003 |
Self-tuning baud rate generator for UART applications The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data... |
| US-7,061,989 |
Fully digital transmitter including a digital band-pass sigma-delta
modulator A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter... |
| US-7,061,820 |
Voltage keeping scheme for low-leakage memory devices The present invention facilitates memory device operation by mitigating power consumption during suspend modes of operation, also referred to as sleep/data... |
| US-7,061,540 |
Programmable display timing generator A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator... |
| US-7,061,512 |
Constant-weight bit-slice PWM method and system for scrolling color
display systems A display system 100 includes a light source 110 and a color wheel 114. An optical section 112 is arranged to receive light from the light source 110 and to... |
| US-7,061,332 |
Process tracking limiter for VCO control voltages A control voltage window generator that tracks process, voltage supply, and temperature variations for a voltage controlled oscillator includes: a first... |
| US-7,061,325 |
Digital compensation for offset and gain correction A system and method for providing digital compensation and correction for an amplifier. The system is configured to provide a digitally compensated ... |
| US-7,061,323 |
Apparatus and method for controlling operation of an amplifier device when
supply voltage varies An apparatus for controlling operation of an amplifier device when supply voltage provided to the amplifier device varies at an input voltage supply locus. The... |
| US-7,061,291 |
Linear voltage tracking amplifier for negative supply slew rate control Circuitry is provided for controlling the slew rate of a negative output supply. The slew rate control circuitry includes an NMOS FET, a feedback resistor... |
| US-7,061,217 |
Integrated power switching circuit A power switching circuit includes a power MOS transistor that has a maximum source-drain voltage substantially higher than a permissible gate-source voltage,... |
| US-7,061,214 |
Single inductor dual output buck converter with frequency and time varying
offset control A single-inductor dual-output buck converter and control method that facilitates power conversion by converting a single DC power source/supply into two separate... |
| US-7,061,204 |
Motor starter device having reduced power consumption A motor starter for use with a motor (20) having a main winding (M) and a start winding (S). The starter has a PTC thermistor (30) connected in series with the... |
| US-7,061,114 |
Structure and method for contact pads having a protected bondable metal
plug over copper-metallized integrated... An integrated circuit having copper interconnecting metallization (311, 312) protected by a first, inorganic overcoat layer (320), portions of the metallization... |
| US-7,061,108 |
Semiconductor device and a method for securing the device in a carrier
tape A method for packing a semiconductor device 301 in a carrier tape 406 without damage to the leads 302 includes an interlocking mechanism between the molded... |
| US-7,061,058 |
Forming a retrograde well in a transistor to enhance performance of the
transistor A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the... |
| US-7,060,633 |
Planarization for integrated circuits A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In... |
| US-7,060,607 |
Circuit method integrating the power distribution functions of the
circuits and leadframes into the chip surface An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are... |
| US-7,060,579 |
Increased drive current by isotropic recess etch A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using... |
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