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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-7,101,772 |
Means for forming SOI A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing. |
| US-7,101,751 |
Versatile system for limiting electric field degradation of semiconductor
structures The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from... |
| US-7,100,813 |
System and method for achieving planar alignment of a substrate during
solder ball mounting for use in... A system (10) and method (30) for precisely depositing a solder compound onto a substrate (18). The system (10) generally includes a receiving member (20) having... |
| US-7,100,151 |
Recovery from corruption using event offset format in data trace A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is... |
| US-7,099,817 |
Stalling CPU pipeline to prevent corruption in trace while maintaining
coherency with asynchronous events A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out... |
| US-7,099,671 |
Collaborative mechanism of enhanced coexistence of collocated wireless
networks A digital device 310 with a plurality of collocated wireless networks encounters inter-network interference if the collocated wireless networks operate in a... |
| US-7,099,414 |
Ordered decoding in wireless communications that utilize turbo coding and
transmit diversity In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol decisions are based at... |
| US-7,099,412 |
Sequential decoding with backtracking and adaptive equalization to combat
narrowband interference Narrowband interference can seriously degrade the overall performance of a communications network without significantly damaging a large percentage of the... |
| US-7,099,353 |
Orthogonal frequency division multiplexing system with superframe
synchronization using correlation sequence A wireless transmitter (TX.sub.1). The transmitter comprises circuitry for providing a plurality of control bits (CONTROL) and circuitry for providing a... |
| US-7,099,270 |
Multi-path equalization for orthogonal frequency division multiplexing
communication system A multi-path equalization system for orthogonal frequency division multiplexing communication (OFDM) system includes a first estimator for estimating the channel... |
| US-7,099,230 |
Virtual ground circuit for reducing SRAM standby power A method of operating a memory circuit having a plurality of blocks of memory cells (400 404) is disclosed. The method includes storing data in the plurality of... |
| US-7,098,833 |
Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate... |
| US-7,098,830 |
Current switching arrangement for D.A.C. reconstruction filtering An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage... |
| US-7,098,826 |
Auto-configuration to connect transmit and receive ports to corresponding
ports on the other end irrespective... An aspect of the present invention provides multiple switches in a transceiver, which enable pins provided for transmission and reception to be connected to... |
| US-7,098,617 |
Advanced programmable closed loop fan control method A fan control system and method that maintains the operating temperature of computer and electronic devices or components at about a predetermined control level... |
| US-7,098,516 |
Refractory metal-based electrodes for work function setting in
semiconductor devices The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate... |
| US-7,098,143 |
Etching method using an at least semi-solid media An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively... |
| US-7,098,099 |
Semiconductor device having optimized shallow junction geometries and
method for fabrication thereof The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide... |
| US-7,098,098 |
Methods for transistors formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate... |
| US-7,098,094 |
NiSi metal gate stacks using a boron-trap A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity... |
| US-7,097,110 |
Temperature compensation systems and methods for use with read/write heads
in magnetic storage devices Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic... |
| US-7,096,649 |
Method and apparatus for integrated circuit storage tube retention pin
removal and insertion While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still... |
| US-7,096,471 |
Apparatus for resource management in a real-time embedded system An apparatus is disclosed for allocating processing resources, such as instruction execution which can be measured in MIPs or memory capacity, or other resources... |
| US-7,096,308 |
LPC transaction bridging across a PCI.sub.--express docking connection A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station.... |
| US-7,096,301 |
Communications interface for enabling extension of an internal common bus
architecture (CBA) A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more... |
| US-7,096,141 |
System and method for testing a device In a method and system for testing a device, a tester is operable to generate a first set of test signals for testing the device. The tester is electrically... |
| US-7,095,987 |
Method and apparatus for received uplinked-signal based adaptive downlink
diversity within a communication system A first downlink transmission beam and a second downlink transmission beam is determined based on a received user-derived signal. The first downlink transmission... |
| US-7,095,819 |
Direct modulation architecture for amplitude and phase modulated signals
in multi-mode signal transmission Multiple-mode direct phase/amplitude modulation circuitry (20) for use in a transceiver (17) of a device such as a wireless handset (10) is disclosed. The... |
| US-7,095,671 |
Electrical fuse control of memory slowdown Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional... |
| US-7,095,594 |
Active read/write head circuit with interface circuit A method and apparatus for collocating an interface circuit with a disk drive read/write head is described. In one embodiment the interface circuit is attached... |
| US-7,095,494 |
Method and apparatus for measuring temporal response characteristics of
digital mirror devices A method and system for measuring the temporal response of a micromirror array to a variety of driving signals. A micromirror array is illuminated with a... |
| US-7,095,356 |
Providing reference voltage with desired accuracy in a short duration to a
dynamically varying load Simplifying the design of buffer amplifier circuits to provide reference voltages of desired characteristics on a path. Two separate circuits may be used to... |
| US-7,095,121 |
Metallic strain-absorbing layer for improved fatigue resistance of
solder-attached devices An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a... |
| US-7,095,105 |
Vertically stacked semiconductor device A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed... |
| US-7,094,650 |
Gate electrode for FinFET device In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs.... |
| US-7,092,827 |
Edge placement accuracy of signals generated by test equipment A software controlled mechanism causing a test equipment to place the edges of test signals accurately. The mechanism determines expected time of occurrence of... |
| US-7,092,537 |
Digital self-adapting graphic equalizer and method A self-adaptive graphic equalizer operable to equalize the affects of an audio system on an audio signal includes an adaptive graphic equalizer having a... |
| US-7,092,276 |
Series feram cell array Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline.... |
| US-7,092,197 |
Rejection of power supply variations for gain error cancellation in
pulse-width-modulated motor controllers A positioning driver (32) for a voice coil motor (22) in a disk drive system (10) is disclosed. Pulse-width-modulated prestage drivers (46) are coupled to power... |
| US-7,092,189 |
Programmable output impedance for hard drive preamplifier write driver A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an... |
| US-7,091,766 |
Retention register for system-transparent state retention State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1-M3; M1-M4) is used to load... |
| US-7,091,556 |
High voltage drain-extended transistor The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a drain-extended... |
| US-7,091,119 |
Encapsulated MOS transistor gate structures and methods for making the
same Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by... |
| US-7,090,787 |
Drying getters A zeolite and an organic binder are mixed with a solvent to form a paste (302). The paste is then cast or molded (304) into the desired shape. A portion of the... |
| US-7,089,447 |
Apparatus and method for compression based error correction procedure in a
data processing system In a data processing system in which the complete set of op-code signal groups are stored in a ROM unit, a programmable, non-volatile memory unit stores the... |
| US-7,089,437 |
Apparatus for determining power consumed by a bus of a digital signal
processor using counted number of logic... In order to measure the power consumed by a bus in a digital signal processor, each bus conductor has a lead electrically coupled thereto. The lead is coupled to... |
| US-7,089,183 |
Accumulating transformations for hierarchical linear regression HMM
adaptation A new iterative hierarchical linear regression method for generating a set of linear transforms to adapt HMM speech models to a new environment for improved... |
| US-7,089,004 |
Method and apparatus for scheduling cell search in CDMA mobile receivers Search scheduling circuitry for use with a wireless communication device, such as a mobile telephone, includes a search time calculator, a search period... |
| US-7,088,791 |
Systems and methods for improving FFT signal-to-noise ratio by identifying
stage without bit growth Systems and methods are provided for performing signal processing on communication data utilizing scale reduced Fast Fourier Transform computations. The present... |
| US-7,088,785 |
Block level space time transmit diversity in wireless communications Space time transmit diversity (9, 14, 17, 19) is applied at the block level to an original block of bits (12) in order to reduce the effects of fading in... |
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