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Patent # Description
US-6,867,653 Apparatus and method for converting a fully-differential class-AB input signal to a rail-to-rail single ended...
An apparatus for converting a fully-differential input signal to an output signal which varies between two rail limits and includes: (a) a first buffer receiving...
US-6,867,652 Fast-response current limiting
An amplifier (10") has a first amplifier stage (14) for producing a control current (I.sub.X) in response to an input voltage. A second amplifier stage (16) has...
US-6,867,503 Controlling interdiffusion rates in metal interconnection structures
A metal interconnection structure for semiconductor chips has a metal interface layer (105), preferably nickel, deposited over the metal of the chip contact pad...
US-6,867,447 Ferroelectric memory cell and methods for fabricating the same
Semiconductor devices and ferroelectric memory cells therefor are provided, where the cells include a ferroelectric capacitor with one or more corners, as well...
US-6,867,100 System for high-precision double-diffused MOS transistors
The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's...
US-6,866,974 Semiconductor process using delay-compensated exposure
A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and...
US-6,865,694 CPU-based system and method for testing embedded memory
A CPU-based system 10 and method for testing embedded memory. The technique employs the on-chip CPU 20 itself to test the embedded memory 24. An assembly code...
US-6,865,504 Apparatus and method for a reconfigurable pod interface for use with an emulator unit
A reconfigurable cable/pod unit replaces the cable/pod unit coupling an emulation unit and a target processor. The reconfigurable cable/pod unit includes the...
US-6,865,222 Method and apparatus for testing a serial transmitter circuit
An integrated circuit (12) contains a serializing transmitter, including a phase locked loop (31) that supplies seven clocks (41) with different phases to a...
US-6,864,818 Programmable bandpass analog to digital converter based on error feedback architecture
A delta sigma modulator based analog to digital converter is presented, having a first quantizer and a digital error feedback system comprising a second...
US-6,864,751 Transimpedance amplifier with adjustable output amplitude and wide input dynamic-range
A transimpedance amplifier circuit comprising transistors, a constant current source, a load resistor, and the feedback resistor with a shunt circuitry...
US-6,864,738 CMOS voltage booster circuits
This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage...
US-6,864,708 Suppressing the leakage current in an integrated circuit
A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the...
US-6,864,702 System for oxide stress testing
The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present...
US-6,864,108 Measurement of wafer temperature in semiconductor processing chambers
A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10)....
US-6,863,401 Illumination system
The addition of DMD illumination modulator(s) 702 in series with projection SLM(s) 706/709 to produce high-performance projection displays with improved optical...
US-6,862,658 Retrieving streams of data from rotating storage medium while balancing various requirements
Parameters characterizing physical operation of a rotating structure (disk drive) are determined by sending appropriate commands and examining the response. The...
US-6,862,640 Arbitration in local system for access to memory in a distant subsystem
A multiprocessor system includes a plurality of data processors. Each data processor includes: a data processing core; a memory forming a local portion of a...
US-6,862,495 In-situ randomization and recording of wafer processing order at process tools
Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing...
US-6,862,398 System for directed molecular interaction in surface plasmon resonance analysis
Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface...
US-6,862,333 CMD and CMD-carrying CCD device
This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such...
US-6,862,275 Cell selection with STTD and SSDT
A method of operating a communication circuit comprises the steps of receiving a plurality of signals (508-509, 514-516) from a plurality of remote transmitters...
US-6,861,901 Voltage follower circuit
A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect...
US-6,861,832 Threshold voltage adjustment for MOS devices
The Vt of an MOS transistor is lowered in response to its load current. In a LDO (low dropout) regulator, lowering the Vt of the pass transistor with load...
US-6,861,826 Timing circuit for synchronous DC/DC control to reduce synchronous rectifier body diode conduction
A control device and method for synchronizing activation and deactivation of a high-side switch (102) and a low-side switch (104) in a converter including an...
US-6,861,721 Barrier region and method for wafer scale package (WCSP) devices
A barrier region provided in the active surface of a wafer-level chip scale package device or chip (WCSP device or chip) to substantially reduce the amount of...
US-6,861,678 Double diffused vertical JFET
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-6,861,608 Process and system to package residual quantities of wafer level packages
Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include...
US-6,861,348 Pre-pattern surface modification of low-k dielectrics
A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction...
US-6,861,303 JFET structure for integrated circuit and fabrication method
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in...
US-6,861,292 Composite lid for land grid array (LGA) flip-chip package assembly
A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back...
US-6,859,899 Method for data packet acquisition using split preamble
A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a...
US-6,859,897 Range based detection of memory access
Memory accesses in a data processing device (14) can be monitored by selecting, from among a plurality of available memory relationships (37, 82), a memory...
US-6,859,852 Immediate grant bus arbiter for bus system
The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect...
US-6,859,814 Transpose FIR filter architecture
A novel Finite Impulse Response ("FIR") filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input...
US-6,859,089 Power switching circuit with controlled reverse leakage
A power switching circuit including an MOS power switching transistor (P1) is disclosed. The power switching transistor (P1) has a body node that is selectably...
US-6,859,020 Low power mode detection circuit for a DC/DC converter
A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a...
US-6,858,910 Method of fabricating a molded package for micromechanical devices
A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process...
US-6,858,908 Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide
A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the...
US-6,858,902 Efficient ESD protection with application for low capacitance I/O pads
A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a...
US-6,858,486 Vertical bipolar transistor formed using CMOS processes
A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect...
US-6,857,751 Adaptive illumination modulator
An image display system includes a light source capable of generating an illumination light beam along an illumination path. The system also includes a modulator...
US-6,857,459 Wirefilm bonding for electronic component interconnection
A system (30) is provided for interconnecting a first component (10) having multiple first bonding sites (16) and a second component (12) having multiple second...
US-6,856,925 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space
When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss...
US-6,856,661 Using phase interpolator information to detect a loss of lock condition during recovery of a clock signal from...
A loss of lock condition of a clock signal (25) recovered from a received data stream can be detected by examining conventionally available information (25, 26)...
US-6,856,655 Timing recovery device and method for telecommunications systems
A timing recovery device for CAP/QAM modems includes an equalizer filter designed to monitor the movement of the filter coefficients within a memory buffer and...
US-6,856,610 Wireless code division multiple access communications system with channel estimation using fingers with...
A wireless communication network (10). The network comprises a wireless receiver (14). The receiver comprises at least one antenna (AT.sub.14) for receiving a...
US-6,856,535 Reference voltage generator for ferroelectric memory
Apparatus and methods are provided for providing reference voltages during read operations in ferroelectric memories, in which a bitline of a reference array...
US-6,856,534 Ferroelectric memory with wide operating voltage and multi-bit storage per cell
Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states...
US-6,856,481 Apparatus and method for providing a read signal for an information processing device
An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information;...
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