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Patent # Description
US-6,831,337 Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge ("ESD")...
A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G.sub.2) in a fixed relationship to the ...
US-6,831,008 Nickel silicide--silicon nitride adhesion through surface passivation
A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel...
US-6,830,980 Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing...
Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during...
US-6,830,956 Method for packaging a low profile semiconductor device
A method to realize low-profile semiconductor devices by grinding a resin sealed block and realize level grinding by eliminating warpage of the resin sealed...
US-6,830,938 Method for improving retention reliability of ferroelectric RAM
The present invention can improve and/or modify data retention lifetimes for ferroelectric devices by baking them prior to or during packaging. A ferroelectric...
US-6,829,759 System and method for generating a translation display
A method for generating a translation display includes receiving a source file (414) including a plurality of source elements (422) and a translation file (418)...
US-6,829,696 Data processing system with register store/load utilizing data packing/unpacking
A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into...
US-6,829,669 Bus bridge interface system
A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance....
US-6,829,626 Computer algebra system and method
A computer algebra system including algebraic expression transformations with a display of domain of definition constraints only when a domain of definition...
US-6,829,598 Method and apparatus for modeling a neural synapse function by utilizing a single conventional MOSFET
A method and apparatus for modeling a neural synapse function in analog hardware whereby the multiplication function inherent to the operation of a neural...
US-6,829,321 High speed and compact overflow detection for shifters
This invention describes a unique high-speed implementation for overflow detection logic to be used in high performance shifter functions. The overflow logic...
US-6,829,307 Express bit swapping in a multicarrier transmission system
Methods and devices for adaptively changing a parameter (such as sub-carrier bit allocation and/or gain) in a multi-carrier communication signal are described....
US-6,829,290 Wireless communications system with combining of multiple paths selected from correlation to the primary...
A wireless receiver (UST). The receiver comprises at least one antenna (ATU) for receiving a plurality of frames (FR) in a form of a plurality of paths. Each of...
US-6,829,016 Digital still camera system and method
A digital image two-step resizing of filtering an entire image followed by selective row and column deletions. The filtering may use a kernel generated as three...
US-6,829,007 Digital scheme for noise filtering of optical black and offset correction in CCD signal processing
An image processing apparatus (800) for a charge coupled device having hot/cold pixel and line noise filtering is disclosed which provides optical black and...
US-6,828,961 Color wheel synchronization in multi-frame-rate display systems
A display system (200) in which light from source (202) is focused onto a spinning color wheel (204). The spinning color wheel (204) spins at a constant rate and...
US-6,828,869 Circuit for temperature determination
A circuit relates to phase and frequency-locked loop circuits (PLL and FLL circuits) with a controllable tracking oscillator whose signal phase relationship or...
US-6,828,856 Amplifier gain boost circuitry and method
A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are...
US-6,828,855 Class AB operational amplifier with split folded-cascode structure and method
Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage (2) of an...
US-6,828,825 Pulse response of fast level shifter
Systems and methods are provided for detecting a state change of a level shifter and actively driving the level shifter into the new state to facilitate the...
US-6,828,797 Alternative method for VOD testing of linear differential line drivers
A method for measuring a test differential voltage across a first output and a second output of a transmitter integrated circuit device, the test differential...
US-6,828,660 Semiconductor device with double nickel-plated leadframe
A leadframe for use in the assembly of integrated circuit (IC) chips, which has first and second surfaces and a base metal structure (606) with an adherent layer...
US-6,828,513 Electrical connector pad assembly for printed circuit board
A connector pad includes projections extending radially outwardly from an inner portion of the pad to help stabilize and reinforce the pad. The added stability...
US-6,828,213 Method to improve STI nano gap fill and moat nitride pull back
A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a...
US-6,828,200 Multistage deposition that incorporates nitrogen via an intermediate step
The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention...
US-6,828,161 Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask...
US-6,827,449 Adhesive-sealed window lid for micromechanical devices
An improved spatial light modulator package comprising a spatial light modulator 1006 attached to a central region of a substrate 1004, a sealing ring 1002 on...
US-6,826,730 System and method for controlling current in an integrated circuit
A circuit 10 is provided that comprises a source resistance transistor 12 connected to a common node 14. A word line driver circuit 18 receives current if it is...
US-6,826,679 Processor with pointer tracking to eliminate redundant memory fetches
A processor is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy...
US-6,826,652 Smart cache
A cache architecture (16) for use in a processing includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in...
US-6,826,527 Concealment of frame erasures and method
A decoder for code excited LP encoded frames with both adaptive and fixed codebooks; erased frame concealment uses muted repetitive excitation, threshold-adapted...
US-6,826,026 Output buffer and I/O protection circuit for CMOS technology
An output circuit for improved ESD protection (FIG. 2) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad 220 and Vdd power supply...
US-6,825,845 Virtual frame buffer control system
A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the...
US-6,825,784 Dithering method for sigma-delta analog-to-digital converters
A Sigma-Delta Analog-to-Digital Converter (ADC) having efficient dithering that removes the idle channel tones of the sigma-delta converter is disclosed herein....
US-6,825,721 Amplifier gain boost circuitry and method
A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are...
US-6,825,706 Multiplexer
A multiplexer containing multiple cells sharing a common output line. The cells select one of multiple input bits. The output line is first charged to a first...
US-6,825,590 Adjustable compensation of a piezo drive amplifier depending on mode and number of elements driven
An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated...
US-6,824,275 Folded projection lens
A projection lens that uses a TIR surface as both an angular filter and fold mirror. A first lens element 602 is placed very close to the TIR prism assembly 604....
US-6,823,652 High density tape carrier system and method of operation
A flexible carrier tape system, suitable for housing components and for winding on a reel in high density, is disclosed, comprising an elongated base strip...
US-6,823,488 Packet binary convolutional codes
A 64-state binary convolutional code is disclosed for a high-speed physical layer (PHY) of a communication network. The proposed code provides improved...
US-6,823,402 Apparatus and method for distribution of signals from a high level data link controller to multiple digital...
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal...
US-6,823,000 Method and apparatus for optimal dot product calculation
A dot product operator (30) uses adder trees (10) of L-1 adders and no multiplication circuits, where L is the length of the parallel dot product operator....
US-6,822,951 Method and apparatus for routing messages in a wireless network
A method and apparatus for routing messages in a wireless network. Transmissions from all devices are synchronized. Each device is equipped with a routing unit...
US-6,822,679 Offset correction to the output of a charge coupled device
The voltage outputs of a charge coupled device (CCD) are examined to determine the hot pixels. A black pixel is determined to be a hot pixel if the voltage level...
US-6,822,509 Differential circuit with a linearity correction loop
A differential circuit with linearity correction loop includes a main differential amplifier 30, and a correction amplifier 20 having inputs coupled to the...
US-6,822,505 Mobility compensation in MOS integrated circuits
A transconductance-setting circuit (10, 20) and method. The circuit (10, 20) includes a first transconductor (14) coupled to a reference voltage (V.sub.ref)...
US-6,822,478 Data-driven clock gating for a sequential data-capture device
A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus...
US-6,822,343 Generating electric power in response to activity of a biological system
A device for generating electricity includes a first portion including a first wall defining a first fluid passage and a second portion including a second wall...
US-6,822,340 Low capacitance coupling wire bonded semiconductor device
A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a...
US-6,822,297 Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness
A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a...
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