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Patent # Description
US-9,344,314 Computer generated sequences for downlink and uplink signals in wireless communication systems
The present disclosure provides a base station transmitter, a user equipment transmitter and methods of operating the base station and user equipment...
US-9,344,097 Fast acquisition frequency detector
A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary...
US-9,344,070 Relaxation oscillator with low drift and native offset cancellation
Relaxation oscillator circuitry is presented with low drift and native offset cancellation, including an amplifier amplifying a first current signal to provide...
US-9,344,066 Digital open loop duty cycle correction circuit
A duty cycle correction (DCC) circuit includes a master delay line that receives an input clock and determines a period of the input clock. A calibration module...
US-9,344,014 Piezoelectric device
Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated...
US-9,343,962 Power regulator system with adaptive ramp signal generator
One embodiment includes a power regulator system. The system includes a switch control stage configured to generate at least one activation signal based on a...
US-9,343,949 Control circuit to detect a noise signal during a state change of a switch
Several circuits and methods for driver control of a switching circuit are disclosed. In an embodiment, a circuit for driver control of a switching circuit...
US-9,343,898 Driver current control apparatus and methods
Apparatus and methods disclosed herein implement steady-state and fast transient electronic current limiting through power transistors, including power...
US-9,343,468 Feed-forward bidirectional implanted split-gate flash memory cell
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second...
US-9,343,459 Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect
Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions...
US-9,343,447 Optically pumped sensors or references with die-to-package cavities
An optoelectronic packaged device includes stacked components within a package including a package substrate providing side and a bottom wall. The stacked...
US-9,343,332 Alignment to multiple layers
A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a...
US-9,342,482 On-chip spectral analysis using enhanced recursive discrete Fourier transforms
A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold...
US-9,342,468 Memory time stamp register external to first and second processors
A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are...
US-9,342,312 Processor with inter-execution unit instruction issue
A processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units...
US-9,342,259 Nonvolatile logic array and power domain segmentation in processing device
A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element...
US-9,342,124 Programmable and simultaneous load switch control for power sequencing
A power delivery and control device that includes a voltage input line, a voltage output line, a control logic unit coupled to the voltage input and voltage...
US-9,342,089 Verification of bandgap reference startup
A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and...
US-9,341,658 Fast on-chip oscillator trimming
Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency...
US-9,341,543 Method and OTDR apparatus for optical cable defect location with reduced memory requirement
Optical time domain reflectometer (OTDR) systems, methods and integrated circuits are presented for locating defects in an optical cable or other optical cable,...
US-9,340,415 MEMS device with non-planar features
A MEMS device is formed with facing surfaces of a contoured substrate and a layer of material having complementary contours. In one fabrication approach, a...
US-9,338,757 Clock synchronization and centralized guard time provisioning
Embodiments of the invention provide a method to accommodate clock drift and guard time in a centralized fashion. In one embodiment, a first device is adapted...
US-9,338,533 Drivers and methods of driving transducers
A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and...
US-9,337,905 Inductive structures with reduced emissions and interference
An inductive structure includes a power coil and a data coil. The data coil is substantially centered within the power coil. A first portion of the data coil...
US-9,337,789 Differential receiver
A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential...
US-9,337,780 Amplifier with sample and hold output and low drive stage
An amplifier (50) for voice or audio signals, and particularly for headset applications, uses a low g.sub.m amplifier (54) for initially charging an output node...
US-9,337,738 Transformer-coupled gate-drive power regulator system
A transformer-coupled gate-drive power regulator system is provided that includes a feedback stage that generates a PWM signal having a duty-cycle that is based...
US-9,337,653 Static MEMS switch for ESD protection
An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD...
US-9,337,330 Scheme to align LDMOS drain extension to moat
An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a...
US-9,337,299 Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p-...
US-9,337,297 Fringe capacitance reduction for replacement gate CMOS
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls...
US-9,337,292 Very high aspect ratio contact
A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the...
US-9,337,130 Leadframe strip and leadframes
A leadframe strip including a first leadframe having a first die pad and a first plurality of generally parallel leads each extending outwardly relative to the...
US-9,337,106 Implant profiling with resist
A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist...
US-9,337,046 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,337,044 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,337,023 Buffer stack for group IIIA-N devices
A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group...
US-9,336,454 Vector processor calculation of local binary patterns
A method (and system) of determining a local binary pattern in an image includes selecting an orientation. For each pixel in the image, the method further...
US-9,336,167 I2C controller register, control, command and R/W buffer queue logic
Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A...
US-9,335,954 Customizable backup and restore from nonvolatile logic array
Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile...
US-9,335,540 MEMS device with improved via support planarization
A microelectromechanical (MEMS) device has a movable member supported above a substrate on a via support. The member and via support are fabricated integrally...
US-9,335,223 Circuits and methods for determining the temperature of a transistor
Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit,...
US-9,333,535 MUT circuit with an electrically controllable membrane
A micromachined ultrasonic transducer (MUT) circuit, which has a MUT with a MUT membrane that can vibrate back and forth to transmit an ultrasonic wave,...
US-9,332,605 Lighting system
A lighting system includes a switch configured so that when the switch is in a first state, current from a supply flows to a light emitter, and when the switch...
US-9,332,515 Mapping schemes for secondary synchronization signal scrambling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-9,331,734 SoC transceiver with single ended/differential modes, tunable capacitor and latch
A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable...
US-9,331,680 Low power clock gated flip-flops
A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan...
US-9,331,591 Primary-side burst mode control scheme for LLC converters
An LLC converter having a primary side burst control circuit, and a secondary side regulator circuit. The primary side burst control circuit has an inner...
US-9,331,582 Volt-second integration cable compensation circuit
A power converter (such as a battery charger) includes a cable configured to deliver a source voltage and current to a load, where the cable is anticipated to...
US-9,331,520 Inductively coupled charger
A device includes a charge controller to regulate a battery output voltage based on an input voltage and an input current received from a charging circuit. A...
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