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Patent # Description
US-6,862,640 Arbitration in local system for access to memory in a distant subsystem
A multiprocessor system includes a plurality of data processors. Each data processor includes: a data processing core; a memory forming a local portion of a...
US-6,862,495 In-situ randomization and recording of wafer processing order at process tools
Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing...
US-6,862,398 System for directed molecular interaction in surface plasmon resonance analysis
Disclosed is apparatus and method for controlled surface plasmon resonance analysis having a surface plasmon resonance sensor (200) with a derivatized surface...
US-6,862,333 CMD and CMD-carrying CCD device
This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such...
US-6,862,275 Cell selection with STTD and SSDT
A method of operating a communication circuit comprises the steps of receiving a plurality of signals (508-509, 514-516) from a plurality of remote transmitters...
US-6,861,901 Voltage follower circuit
A voltage follower comprising a first field-effect transistor (MN1) whose gate forms the input of the voltage follower. Further provided is a second field-effect...
US-6,861,832 Threshold voltage adjustment for MOS devices
The Vt of an MOS transistor is lowered in response to its load current. In a LDO (low dropout) regulator, lowering the Vt of the pass transistor with load...
US-6,861,826 Timing circuit for synchronous DC/DC control to reduce synchronous rectifier body diode conduction
A control device and method for synchronizing activation and deactivation of a high-side switch (102) and a low-side switch (104) in a converter including an...
US-6,861,721 Barrier region and method for wafer scale package (WCSP) devices
A barrier region provided in the active surface of a wafer-level chip scale package device or chip (WCSP device or chip) to substantially reduce the amount of...
US-6,861,678 Double diffused vertical JFET
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-6,861,608 Process and system to package residual quantities of wafer level packages
Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include...
US-6,861,348 Pre-pattern surface modification of low-k dielectrics
A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction...
US-6,861,303 JFET structure for integrated circuit and fabrication method
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in...
US-6,861,292 Composite lid for land grid array (LGA) flip-chip package assembly
A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back...
US-6,859,899 Method for data packet acquisition using split preamble
A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a...
US-6,859,897 Range based detection of memory access
Memory accesses in a data processing device (14) can be monitored by selecting, from among a plurality of available memory relationships (37, 82), a memory...
US-6,859,852 Immediate grant bus arbiter for bus system
The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect...
US-6,859,814 Transpose FIR filter architecture
A novel Finite Impulse Response ("FIR") filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input...
US-6,859,089 Power switching circuit with controlled reverse leakage
A power switching circuit including an MOS power switching transistor (P1) is disclosed. The power switching transistor (P1) has a body node that is selectably...
US-6,859,020 Low power mode detection circuit for a DC/DC converter
A DC/DC converter has a semiconductor switch coupled to an inductor, a capacitor and a rectifier. A comparator is coupled to across the rectifier to detect a...
US-6,858,910 Method of fabricating a molded package for micromechanical devices
A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process...
US-6,858,908 Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide
A method of forming a first and second transistor. The method provides a semiconductor surface (20). The method also forms a gate dielectric (30) adjacent the...
US-6,858,902 Efficient ESD protection with application for low capacitance I/O pads
A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a...
US-6,858,486 Vertical bipolar transistor formed using CMOS processes
A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect...
US-6,857,751 Adaptive illumination modulator
An image display system includes a light source capable of generating an illumination light beam along an illumination path. The system also includes a modulator...
US-6,857,459 Wirefilm bonding for electronic component interconnection
A system (30) is provided for interconnecting a first component (10) having multiple first bonding sites (16) and a second component (12) having multiple second...
US-6,856,925 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space
When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss...
US-6,856,661 Using phase interpolator information to detect a loss of lock condition during recovery of a clock signal from...
A loss of lock condition of a clock signal (25) recovered from a received data stream can be detected by examining conventionally available information (25, 26)...
US-6,856,655 Timing recovery device and method for telecommunications systems
A timing recovery device for CAP/QAM modems includes an equalizer filter designed to monitor the movement of the filter coefficients within a memory buffer and...
US-6,856,610 Wireless code division multiple access communications system with channel estimation using fingers with...
A wireless communication network (10). The network comprises a wireless receiver (14). The receiver comprises at least one antenna (AT.sub.14) for receiving a...
US-6,856,535 Reference voltage generator for ferroelectric memory
Apparatus and methods are provided for providing reference voltages during read operations in ferroelectric memories, in which a bitline of a reference array...
US-6,856,534 Ferroelectric memory with wide operating voltage and multi-bit storage per cell
Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states...
US-6,856,481 Apparatus and method for providing a read signal for an information processing device
An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information;...
US-6,856,480 Phase tolerant servo gray code detector
Methods and apparatus are disclosed for detecting PR4 equalized Gray codes, providing phase tolerant Gray codes and detection thereof. A Gray code detector is...
US-6,856,464 Color splitting apparatus and method with unequal glass path lengths
A three element prism system and method for splitting/combining three different colors of light arranged such that the size of a selected one of the color prism,...
US-6,856,446 Digital micromirror device having mirror-attached spring tips
A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of three operating layers 12, 13, 14. An addressing layer 12 is...
US-6,856,264 Method for decoding reversible variable length code using leading-zeros variable length decoding techniques
A method for decoding a bitstream of reversible variable length codewords parses the bitstream to extract a next reversible variable length codeword, transcodes...
US-6,856,195 Preamplifier system with selectable input impedance
Systems and methods are provided for selecting an input impedance of a preamplifier device. Multiple feedback paths are provided to an amplifier device of the...
US-6,856,188 Current source/sink with high output impedance using bipolar transistors
A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by...
US-6,856,174 Versatile system for high resolution device calibration
The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the...
US-6,856,143 System and method for measuring a capacitance of a conductor
A method for measuring a capacitance of a device under test is provided that includes selectively charging and discharging a first conductor with a first set of...
US-6,856,120 Regulator circuit
A regulator circuit capable of reducing an increase in an output voltage during a sudden drop in a load current without increasing the power consumption during a...
US-6,856,117 Detection circuit having an adaptive threshold
A voltage detection circuit utilizes a comparator to compare first and second input voltages to generate a control signal when the difference between the first...
US-6,856,014 Method for fabricating a lid for a wafer level packaged optical MEMS device
A method of individually packaging a multiplicity of devices, such as a spatial light modulator, before the multiplicity of devices formed on a substrate wafer...
US-6,856,000 Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit...
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively...
US-6,855,984 Process to reduce gate edge drain leakage in semiconductor devices
The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted...
US-6,855,578 Vibration-assisted method for underfilling flip-chip electronic devices
A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less...
US-6,854,076 Method and apparatus for calibration of an electronic device
A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high...
US-6,854,001 Apparatus and method for simultaneously displaying a number along with its number of significant figures
A computing device (40) comprises an electrical circuit and a software application. A display screen (138) and an input device (140) are electrically coupled to...
US-6,853,715 Provisioning of subscriber services
A system for provisioning of enhanced telephone services by the subscriber is provided for a base telephone account. The system allows enhanced services that are...
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