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Patent # Description
US-6,806,762 Circuit and method to facilitate threshold voltage extraction and facilitate operation of a capacitor multiplier
A system and method to extract a threshold voltage for a MOSFET include first and second stages, which include inputs that receive functionally related input...
US-6,806,690 Ultra-low quiescent current low dropout (LDO) voltage regulator with dynamic bias and bandwidth
An LDO regulator automatically switches from the SLEEP mode to the ON mode without the need for an externally generated control signal. The LDO regulator...
US-6,806,541 Field effect transistor with improved isolation structures
An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and...
US-6,806,196 High precision integrated circuit capacitors
A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer...
US-6,806,195 Manufacturing method of semiconductor IC device
To provide a manufacturing method of the semiconductor IC device having fine-structure connecting holes or trenches with high dimensional precision. There is the...
US-6,806,193 CMP in-situ conditioning with pad and retaining ring clean
A method for preconditioning a CMP polishing pad and retaining ring prior to semiconductor wafer polishing. In the method of the present invention, the retaining...
US-6,806,159 Method for manufacturing a semiconductor device with sinker contact region
A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a...
US-6,806,151 Methods and apparatus for inducing stress in a semiconductor device
Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce...
US-6,806,149 Sidewall processes using alkylsilane precursors for MOS transistor fabrication
A method for using alkylsilane precursors during the sidewall formation process in MOS transistor fabrication processes. Alkylsilane precursors are used to form...
US-6,806,103 Method for fabricating semiconductor devices that uses efficient plasmas
The present invention provides, in one embodiment, process of treating a target semiconductor surface. The process includes exposing a test surface to a plasma...
US-6,806,101 Ferroelectric capacitor plasma charging monitor
Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having...
US-6,805,614 Multilayered CMP stop for flat planarization
A three layer film (116/114/112), such as nitride/oxide/nitride for a CMP stop layer (110). A gap filling material (120) is polished, stopping on the first film...
US-6,804,725 IC with state machine controlled linking module
A TAP linking module provides for control and access of plural TAPs on an IC through one set of JTAG signal pins. The IC includes plural circuit modules, each...
US-6,804,697 Circuit for precise measurement of the average value of the outputs of multiple circuit unit elements
An averaging circuit includes: input signal nodes for providing input signals 330; a multiplexing circuit 320 coupled to the input signal nodes for switching...
US-6,804,311 Diversity detection for WCDMA
A circuit for detecting a transmit diversity signal comprises a first circuit (706) arranged to receive a first synchronization code. The first synchronization...
US-6,804,291 Device and method of digital gain programming using sigma-delta modulator
A sigma delta modulator (350) can be utilized in the Digital-to-Analog (DAC) portion (144) of a modem (120) to achieve a desired level of gain programming. A set...
US-6,804,244 Integrated circuits for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,804,243 Hardware acceleration for segmentation of message packets in a universal serial bus peripheral device
A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB...
US-6,804,141 Dynamic reference voltage calibration integrated FeRAMS
A FeRAM includes a reference voltage calibration circuit that evaluates FeRAM cells and selects reference voltages for reading the FeRAM cells. Calibration of...
US-6,804,095 Drain-extended MOS ESD protection structure
A protection structure (30; 30'; 30") for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure...
US-6,803,938 Dynamic laser printer scanning alignment using a torsional hinge mirror
In a laser printer which uses a scanning mirror 12 with torsional hinges 36A, 36B driven by electrical coils 30A, 30B to provide resonant pivoting, at least one...
US-6,803,830 Phase-locked loop and method for automatically setting its output frequency
A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a...
US-6,803,811 Active hybrid circuit
A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a...
US-6,803,661 Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography
A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an...
US-6,803,641 MIM capacitors and methods for fabricating same
Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling...
US-6,803,611 Use of indium to define work function of p-type doped polysilicon
The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate...
US-6,803,295 Versatile system for limiting mobile charge ingress in SOI semiconductor structures
Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the...
US-6,803,282 Methods for fabricating low CHC degradation mosfet transistors
Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions...
US-6,803,273 Method to salicide source-line in flash memory with STI
A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming...
US-6,802,987 Integrated circuit ferroelectric infrared detector and method
Ferroelectric materials useful in monolithic uncooled infrared imaging use Ca and Sn substitutions in PbTiO3 and also have alternatives with dopants such as Dy,...
US-6,802,119 Conductive pedestal on pad for leadless chip carrier (LCC) standoff
A device and method for insuring the separation between a leadless chip carrier and printed wiring board, comprising aligning and attaching conductive pedestals...
US-6,801,985 Data bus using synchronous fixed latency loop including read address and data busses and write address and data...
Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus...
US-6,801,958 Method and system for data transfer
According to one embodiment of the present invention, a system (10) for data transfer is disclosed that comprises a transfer memory (24) having one or more...
US-6,801,922 Sampling rate converter and method
Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated...
US-6,801,588 Combined channel and entropy decoding
A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional...
US-6,801,567 Frequency bin method of initial carrier frequency acquisition
A frequency bin method of carrier frequency acquisition uses a plurality of predetermined carrier frequency offset bins. A single bin is selected from among the...
US-6,801,532 Packet reconstruction processes for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,801,499 Diversity schemes for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,801,461 Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores...
US-6,801,116 Overload protector with hermetically sealing structure
Disclosed is an overload protector with a hermetically sealed structure, the overload protector comprising a housing that has an outer peripheral flange and an...
US-6,801,075 Method and circuit for base current compensation
A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a...
US-6,801,058 Circuit and method for over-current sensing and control
The present invention comprises a low side reverse recovery sense circuit (401) and a high side reverse recovery sense circuit (601), of a low side over-current...
US-6,801,057 Silicon-on-insulator dynamic logic
The SOI dynamic logic circuits comprises series and parallel pull-down networks (260) that comprise MOS transistors configured in series or parallel. Each pull...
US-6,800,944 Power/ground ring substrate for integrated circuits
A substrate (110) for an unpackaged integrated circuit (IC) chip (118). The substrate comprises an insulative material (112), a plurality of contacts (114)...
US-6,800,928 Porous integrated circuit dielectric with decreased surface porosity
A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling...
US-6,800,917 Bladed silicon-on-insulator semiconductor devices and method of making
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and...
US-6,800,555 Wire bonding process for copper-metallized integrated circuits
A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated...
US-6,800,547 Integrated circuit dielectric and method
A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling...
US-6,800,523 Integrated DRAM process/structure using contact pillars
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The...
US-6,799,266 Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as...
A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a...
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