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Apparatus and method for a peripheral inter-module event communication
An inter-module communication system provides for the exchange of status/event signals between interface modules monitoring the activity of external apparatus....
Accuracy determination in bit line voltage measurements
A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense...
A quadrature divider includes a first analog mixer (20, 30) for receiving a digital input signal at a predetermined frequency at a first input of the mixer and a...
Compact, high power supply rejection ratio, low power semiconductor
digitally controlled oscillator architecture
A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of...
Apparatus and method for indicating a difference between first and second
An apparatus for indicating a difference between a first voltage and a second voltage includes: (a) an input unit for receiving the first voltage at a first...
All digital transistor high gain operational amplifier using positive
A new all digital transistor CMOS very high DC-gain amplifier (30) that uses an internal positive-feedback technique. This amplifier (30) does not require...
Glitch free clock multiplexing circuit with asynchronous switch control and
minimum switch over time
A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other...
Thermally enhanced semiconductor chip having integrated bonds over active
An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude...
Composite lid for land grid array (LGA) flip-chip package assembly
A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back...
Gate structure and method
CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si--SiGe emitter-base junctions.
Circuit and method for an integrated charged device model clamp
A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface...
Line self protecting multiple output power IC architecture
A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to...
Compact image sensor layout with charge multiplying register
The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication...
Integrated circuit dielectric and method
A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a...
Method for improved cu electroplating in integrated circuit fabrication
The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential...
Copper surface passivation during semiconductor manufacturing
An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper...
Flash memory cell process using a hardmask
A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch...
Method of dicing a semiconductor wafer and heat sink into individual
semiconductor integrated circuits
A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a...
Gate structure and method
MOSFET fabrication methods with high-k gate dielectrics for silicon or metal gates with gate dielectric deposition control including TXRF. TXRF permits analysis...
Edge-sealed pad for CMP process
The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process...
Hermetic pressure transducer
A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal...
Decision-directed adaptation for coded modulation
A method and apparatus for decision-directed adaptation for coded modulation is presented in which a modulation decoder and data re-encoder are used to create an...
Anti-fuse structure and method of writing and reading in integrated
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an...
Capacitive pressure transducer
A capacitive fluid pressure transducer (10') has a sensing element (12) received in an electrically conductive cup-shaped shield member (24) which is crimped...
Threshold screening using range reduction
A screening method in a printer for approximating a gray scale tone with a more limited range image producer using a tree search. An input pixel packed data word...
Vertical compensation in a moving camera
A hand-held device comprising a housing (10) shaped and dimensioned to allow the device to be hand held, a display (12) secured to the housing for displaying...
Dual-stage digital-to-analog converter
A dual-stage DAC system is provided that includes a coarse resistor network having a first portion and a second portion that provide a plurality of segment...
Low voltage amplifier
An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier...
Flip flop with reduced leakage current
A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors...
Spreading the power dissipation in MOS transistors for improved ESD
An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid...
Analysis of MEMS mirror device using a laser for mirror removal
A method of analyzing a MEMS device having micromirrors. A laser is targeted on one or more mirror elements and used to remove only the mirror. Once the mirror...
Etch back of interconnect dielectrics
An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric...
Method of manufacturing a semiconductor chip comprising multiple bonding
pads in staggard rows on edges
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is...
Undulated moat for reducing contact resistance
The present invention includes a method of forming a semiconductor device.
Method for annealing ultra-thin, high quality gate oxide layers using
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a...
Method of forming a semiconductor device package using a plate layer
surrounding contact pads
A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive...
Selective deposition of emissive layer in electroluminescent displays
A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88)...
Gradient dragout system in a continuous plating line
An enhanced gradient dragout system conserves plating chemicals, including precious metals by providing a series of tanks with cascading rinse solutions having a...
System and method for integrated oxide removal and processing of a
An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single ...
IC with two state machines connected to serial scan path
A serial scan architecture (102-126) provides improved processor emulation capability.
TLB operation based on task-ID
A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation...
Hearing assist device with directional detection and sound modification
A hearing assist device (10) for a person (P). The device comprises a speaker device (SP1) for presenting sound to an ear canal of the person and circuitry for...
A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first...
Method and apparatus for digital camera real-time image correction in
A method for previewing an image in a camera prior to output. The method includes steps of gathering image data, storing the image data, calculating display...
Display operation with inserted block clears
An SLM PWM clocking method, called "jog clear," for generating short bit periods where block data clears (74) are inserted between block data loads (72, 76)...
Canceling feedback resister loading effect in a shunt-shunt feedback
A shunt-shunt feedback current to voltage converter (60) including a compensating current (22) provided to the output of the amplifier (12) which mirrors the...
CMOS differential amplifier
A Complementary CMOS differential amplifier has automatic operating point adjustment (self-biasing) and the properties of a rail-to-rail amplifier. The CMOS...
High PSRR current source
The present invention improves on the topology of a conventional current source by interposing an RC circuit and additional MOS between the output of a buffer...
Circuit and method for removing increased power supply current spike that
occurs during initial turn-on or...
A method and circuit (55) are presented for reducing a current spike (9) created after a commutation of a driving current of a polyphase motor (14). The motor...
Method to improve silicide formation on polysilicon
A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of...