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Patent # Description
US-6,819,144 Latched sense amplifier with full range differential input voltage
A sense amplifier that is capable of sensing small differential voltage between two inputs with full voltage range includes a first inverter 305 and 306; a...
US-6,819,123 Extraction of interconnect parasitics
The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect...
US-6,819,072 Disk drive servo arm retract and spindle brake circuit
A spindle motor control circuit for controlling a motor; including a control circuit to control the motor during at least a low state, a pulse state and a high...
US-6,818,966 Method and structure for controlling surface properties of dielectric layers in a thin film component for...
A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming...
US-6,818,540 Fine pitch system and method for reinforcing bond pads in semiconductor devices
A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the...
US-6,818,526 Method for moat nitride pull back for shallow trench isolation
A method of fabricating a shallow trench isolation structure includes forming outwardly of a semiconductor layer a first oxide layer. A nitride layer is formed...
US-6,818,518 Method for producing low/high voltage threshold transistors in semiconductor processing
The present invention provides a system and method for processing low voltage threshold transistors on a semiconductor wafer. The method may include: forming...
US-6,816,921 Micro-controller direct memory access (DMA) operation with adjustable word size transfers and address...
A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the...
US-6,816,796 Resistance measuring circuit
In the resistance measuring circuit, a measuring capacitor (Cm), as controlled by a microcomputer (10), is charged in a first cycle to a predefined charging...
US-6,816,640 Optical add drop multiplexer
An optical switch ideally suited for use as an optical add drop multiplexer (OADM). A light beam entering the OADM through a first input fiber (402) is separated...
US-6,816,553 Coding method for an image signal
To provide high quality coding with respect to both interlace video and progressive video. It is a coding method for image signals, which includes the steps of...
US-6,816,541 Spread spectrum interference cancellation
Iterative parallel interference cancellation estimations for signals received from multiple coded sources or a source with multiple coded outputs with updated...
US-6,816,375 Heat sink attachment
A new heat sink apparatus and method that simplify the assembly of the heat sink and thermal stud. The new heat sink assembly uses a spring retainer that, in...
US-6,816,184 Method and apparatus for mapping a location from a video image to a map
A monitoring system (10) includes a video camera (12) which generates images of a monitored area. A computer (16) receives the images from the video camera, and...
US-6,816,004 Minimizing noise in data channels implemented using frequency division multiplexing
A filter circuit with two 2.sup.nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is...
US-6,816,000 Booster circuit
The objective of the invention is to provide a booster circuit with reduced power consumption and switching noise. Booster circuit 1 of the present invention has...
US-6,815,970 Method for measuring NBTI degradation effects on integrated circuits
A method of testing integrated circuits for the effect of NBTI degradation. A static DC stress voltage is applied to the voltage supply input of the circuit....
US-6,815,836 Wire bonding for thin semiconductor package
An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact...
US-6,815,801 Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer
The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical...
US-6,815,757 Single-poly EEPROM on a negatively biased substrate
Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be...
US-6,815,742 System with meshed power and signal buses on cell array
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a...
US-6,815,276 Segmented power MOSFET of safe operation
Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and...
US-6,814,445 DMD heat sink socket assembly
A method for removing heat from a spatial light modulator device in a digital projection display by encapsulating the device package in a thermal conductive...
US-6,813,757 Method for evaluating a mask pattern on a substrate
A method for evaluating a mask pattern for a product that is manufactured by a process that is described at least in part by a mathematical process model...
US-6,813,738 IC test cell with memory output connected to input multiplexer
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for...
US-6,813,446 System for acquiring and maintaining reliable optical wireless links
Disclosed is apparatus and method for establishing and maintaining optical data transfer between a first optical communications device (202) and a second optical...
US-6,813,111 Implementation method of digital phase-locked loop
A phase lock loop to control phase error including a first phase error detector to detect the phase error in a first mode, a first loop filter to filter a first...
US-6,813,087 Multi-mode color filter
A multi-mode color filter 400 having an inner hub region 402 used to mount the color filter 400 to a motor shaft. A first track 404 and a second track 406 of...
US-6,812,793 Power supply rejection circuit for an audio amplifier
A circuit for power amplification for an audio amplifier that reduces power supply noise amplified to the load. The circuit takes the prior art circuit's...
US-6,812,782 Switch mode converter that allows 100% duty cycle on gate driver
A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry....
US-6,812,678 Voltage independent class A output stage speedup circuit
A low drop-out voltage regulator circuit includes: a MOS pass through transistor 12; a resistor feedback circuit 18 and 20 coupled to the MOS pass through...
US-6,812,676 DC-DC converter and controller for DC-DC converter
A DC--DC converter prevents reverse current from flowing through the inductor, suppresses ringing noise in the low-load state, lowers the power consumption, and...
US-6,812,671 Method and apparatus for controlling current draw while charging a battery array
An apparatus for use with a charge control system for affecting current draw from a charging unit coupled at an input locus of the charge control system for...
US-6,812,669 Resonant scanning mirror driver circuit
A micro-electro-mechanical system (MEMS) resonant scanning mirror driver circuit has separate amplitude and waveshape inputs which allows a relatively slow and...
US-6,812,590 Power supply circuit
External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector...
US-6,812,562 Method and apparatus for surface mounted power transistor with heat sink
A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on...
US-6,812,477 Integrated circuit identification
A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor...
US-6,812,073 Source drain and extension dopant concentration
A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at...
US-6,812,050 System and method of evaluating gate oxide integrity for semiconductor microchips
The present invention provides a system and method for evaluating gate oxide integrity in a semiconductor wafer. The system may include: a semiconductor wafer; a...
US-6,811,669 Methods and apparatus for improved current density and feature fill control in ECD reactors
Apparatus and methods are disclosed for electroplating conductive films on semiconductor wafers, wherein field adjustment apparatus is located in a reservoir...
US-6,810,520 Programmable multi-standard MAC architecture
The present invention provides a method, system and apparatus for managing data flow over an open system interconnection type network (10) which includes a...
US-6,810,475 Processor with pipeline conflict resolution using distributed arbitration and shadow registers
A processing engine including a processor pipeline 820 with a number of pipeline stages, a number of resources and a pipeline protection mechanism. The pipeline...
US-6,810,044 Order broadcast management (IOBMAN) scheme
The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of...
US-6,809,954 Circuit and method for reducing access transistor gate oxide stress
A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first 106 and...
US-6,809,598 Hybrid of predictive and closed-loop phase-domain digital PLL architecture
A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in...
US-6,809,590 Output stage using positive feedback to provide large current sourcing capability
An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP2 is mirrored by...
US-6,809,556 Self-compensating glitch free clock switch
A glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity...
US-6,809,394 Dual metal-alloy nitride gate electrodes
An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190....
US-6,809,370 High-k gate dielectric with uniform nitrogen profile and methods for making the same
High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is...
US-6,808,997 Complementary junction-narrowing implants for ultra-shallow junctions
Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include...
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