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Patent # Description
US-6,788,074 System and method for using a capacitance measurement to monitor the manufacture of a semiconductor
A method for measuring a capacitance of a semiconductor is provided that includes positioning a measurement circuit in a scribe line area associated with the...
US-6,787,875 Self-aligned vias in an integrated circuit structure
A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one...
US-6,787,469 Double pattern and etch of poly with hard mask
A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a...
US-6,787,425 Methods for fabricating transistor gate structures
Methods are presented for fabricating MOS transistors, in which a sacrificial material such as silicon germanium is formed over a gate contact material prior to...
US-6,787,397 Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in ...
US-6,787,187 Micromechanical device fabrication
A method of fabricating a micromechanical device. Several of the micromechanical devices are fabricated 20 on a common wafer. After the devices are fabricated,...
US-6,786,978 Mass production of cross-section TEM samples by focused ion beam deposition and anisotropic etching
A method of preparing a TEM sample. A focused ion beam is used to deposit a mask on the material to be sampled. Reactive ion etching removes material not...
US-6,786,411 Image sensor array readout for simplified image compression
The pixels of an image sensor array can be readout (84, 85) in m.times.n blocks (m, n) that are compatible with the operation of a desired image compression...
US-6,785,878 Correcting a mask pattern using multiple correction grids
Correcting a mask pattern includes accessing a record associated with an uncorrected pattern that comprises segments. The record associates each segment with a...
US-6,785,859 Interleaver for variable block size
An interleaver structure for turbo codes with variable block size. The interleaver permutes symbols through multiplication by a parameter followed by modulus by...
US-6,785,850 System and method for automatically configuring a debug system
The invention relates to a software system and method for configuring a software system for interaction with a hardware system. In this method, the software...
US-6,785,749 Apparatus and method for a peripheral inter-module event communication system
An inter-module communication system provides for the exchange of status/event signals between interface modules monitoring the activity of external apparatus....
US-6,785,629 Accuracy determination in bit line voltage measurements
A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense...
US-6,785,528 Quadrature divider
A quadrature divider includes a first analog mixer (20, 30) for receiving a digital input signal at a predetermined frequency at a first input of the mixer and a...
US-6,784,755 Compact, high power supply rejection ratio, low power semiconductor digitally controlled oscillator architecture
A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of...
US-6,784,736 Apparatus and method for indicating a difference between first and second voltage signals
An apparatus for indicating a difference between a first voltage and a second voltage includes: (a) an input unit for receiving the first voltage at a first...
US-6,784,734 All digital transistor high gain operational amplifier using positive feedback technique
A new all digital transistor CMOS very high DC-gain amplifier (30) that uses an internal positive-feedback technique. This amplifier (30) does not require...
US-6,784,699 Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time
A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other...
US-6,784,539 Thermally enhanced semiconductor chip having integrated bonds over active circuits
An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude...
US-6,784,535 Composite lid for land grid array (LGA) flip-chip package assembly
A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back...
US-6,784,507 Gate structure and method
CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si--SiGe emitter-base junctions.
US-6,784,496 Circuit and method for an integrated charged device model clamp
A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface...
US-6,784,493 Line self protecting multiple output power IC architecture
A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to...
US-6,784,412 Compact image sensor layout with charge multiplying register
The image sensing device incorporates a charge multiplication function in its serial register. The design layout is compact in size and the charge multiplication...
US-6,784,121 Integrated circuit dielectric and method
A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a...
US-6,784,104 Method for improved cu electroplating in integrated circuit fabrication
The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential...
US-6,784,093 Copper surface passivation during semiconductor manufacturing
An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper...
US-6,784,056 Flash memory cell process using a hardmask
A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch...
US-6,784,022 Method of dicing a semiconductor wafer and heat sink into individual semiconductor integrated circuits
A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a...
US-6,783,997 Gate structure and method
MOSFET fabrication methods with high-k gate dielectrics for silicon or metal gates with gate dielectric deposition control including TXRF. TXRF permits analysis...
US-6,783,437 Edge-sealed pad for CMP process
The present invention discloses a polishing pad that can facilitate process stability, extend length of use, and mitigate process non-uniformity and process...
US-6,782,758 Hermetic pressure transducer
A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal...
US-6,782,046 Decision-directed adaptation for coded modulation
A method and apparatus for decision-directed adaptation for coded modulation is presented in which a modulation decoder and data re-encoder are used to create an...
US-6,781,887 Anti-fuse structure and method of writing and reading in integrated circuits
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an...
US-6,781,814 Capacitive pressure transducer
A capacitive fluid pressure transducer (10') has a sensing element (12) received in an electrically conductive cup-shaped shield member (24) which is crimped...
US-6,781,717 Threshold screening using range reduction
A screening method in a printer for approximating a gray scale tone with a more limited range image producer using a tree search. An input pixel packed data word...
US-6,781,623 Vertical compensation in a moving camera
A hand-held device comprising a housing (10) shaped and dimensioned to allow the device to be hand held, a display (12) secured to the housing for displaying...
US-6,781,536 Dual-stage digital-to-analog converter
A dual-stage DAC system is provided that includes a coarse resistor network having a first portion and a second portion that provide a plurality of segment...
US-6,781,463 Low voltage amplifier
An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier...
US-6,781,411 Flip flop with reduced leakage current
A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors...
US-6,781,204 Spreading the power dissipation in MOS transistors for improved ESD protection
An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid...
US-6,781,094 Analysis of MEMS mirror device using a laser for mirror removal
A method of analyzing a MEMS device having micromirrors. A laser is targeted on one or more mirror elements and used to remove only the mirror. Once the mirror...
US-6,780,756 Etch back of interconnect dielectrics
An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric...
US-6,780,749 Method of manufacturing a semiconductor chip comprising multiple bonding pads in staggard rows on edges
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is...
US-6,780,742 Undulated moat for reducing contact resistance
The present invention includes a method of forming a semiconductor device.
US-6,780,719 Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a...
US-6,780,673 Method of forming a semiconductor device package using a plate layer surrounding contact pads
A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive...
US-6,780,662 Selective deposition of emissive layer in electroluminescent displays
A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88)...
US-6,780,253 Gradient dragout system in a continuous plating line
An enhanced gradient dragout system conserves plating chemicals, including precious metals by providing a series of tanks with cascading rinse solutions having a...
US-6,780,250 System and method for integrated oxide removal and processing of a semiconductor wafer
An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single ...
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