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Patent # Description
US-6,856,117 Detection circuit having an adaptive threshold
A voltage detection circuit utilizes a comparator to compare first and second input voltages to generate a control signal when the difference between the first...
US-6,856,014 Method for fabricating a lid for a wafer level packaged optical MEMS device
A method of individually packaging a multiplicity of devices, such as a spatial light modulator, before the multiplicity of devices formed on a substrate wafer...
US-6,856,000 Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit...
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively...
US-6,855,984 Process to reduce gate edge drain leakage in semiconductor devices
The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted...
US-6,855,578 Vibration-assisted method for underfilling flip-chip electronic devices
A semiconductor assembly comprising an integrated circuit chip with a first plurality of metallic contact pads exposed, having a pitch center-to-center of less...
US-6,854,076 Method and apparatus for calibration of an electronic device
A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high...
US-6,854,001 Apparatus and method for simultaneously displaying a number along with its number of significant figures
A computing device (40) comprises an electrical circuit and a software application. A display screen (138) and an input device (140) are electrically coupled to...
US-6,853,715 Provisioning of subscriber services
A system for provisioning of enhanced telephone services by the subscriber is provided for a base telephone account. The system allows enhanced services that are...
US-6,853,574 Reducing leakage current in circuits implemented using CMOS transistors
Reducing leakage current when a circuit contains a series of CMOS transistors. The probability that each input signal (connecting to the gate terminal of the...
US-6,853,510 High-speed low-capacitive load common mode feedback
A variable gain amplifier to output a differential output signal includes an input circuit to input a differential input signal, a buffer circuit to buffer the...
US-6,853,212 Gated scan output flip-flop
A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage...
US-6,853,178 Integrated circuit leadframes patterned for measuring the accurate amplitude of changing currents
A metallic leadframe for use with a semiconductor chip intended for operation in a changing magnetic field comprises a chip mount pad having at least one slit...
US-6,853,170 DC-DC converter and DC-DC converter drive circuit
The objective of this invention is to provide a DC-DC converter characterized by the fact that by correcting the loop gain corresponding to the switching of the...
US-6,852,645 High temperature interface layer growth for high-k gate dielectric
The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture...
US-6,852,603 Fabrication of abrupt ultra-shallow junctions
One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity...
US-6,851,493 Digital PLL with gear shift
A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, .alpha.. During frequency/phase acquisition, a larger loop gain constant,...
US-6,851,270 Integrated refrigeration control
An integrated refrigeration control (IRC) module is disclosed which combines both thermal and electrical protection to the main components of a refrigerator and...
US-6,851,072 Fault management and recovery based on task-ID
In accordance with a first embodiment of the invention, there is provided a method of operating a digital system that has a processor and a memory. A plurality...
US-6,850,877 Worst case performance modeling of analog circuits
A computer system (30) and method of operating the same to model worst case performances of an analog circuit is disclosed. The computer system (30) includes...
US-6,850,104 Master-slave latch with transparent mode
A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the...
US-6,850,103 Low leakage single-step latch circuit
This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch...
US-6,850,045 Multi-phase and multi-module power system with a current share bus
A pulse width modulator (305) for driving a load in a multi-phased power system having circuitry (270) responsive to channel signals for providing an average...
US-6,849,944 Using a supporting structure to control collapse of a die towards a die pad during a reflow process for...
In one embodiment, an integrated circuit package includes a die associated with an integrated circuit and a die pad. The die has a bottom surface, and the pad...
US-6,849,806 Electrical apparatus having resistance to atmospheric effects and method of manufacture therefor
An electrical apparatus having resistance to atmospheric effects includes at least one electrical device and a packaging structure. The packaging structure...
US-6,849,528 Fabrication of ultra shallow junctions from a solid source with fluorine implantation
One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity...
US-6,848,928 Socket
A test socket 10 of the present invention includes a base member 20, a cover member 30 which is installed on base 20 to move in reciprocal straight line movement...
US-6,848,092 Layout of networks using parallel and series elements
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically...
US-6,848,066 Error reduction in semiconductor processes
A photolithography system includes a photolithography tool 32 that includes a stage upon which a semiconductor wafer is mounted. The tool is operable to move the...
US-6,848,054 Real-time computer thermal management and power conservation
A real-time thermal management and power conservation apparatus and method for computers employs a monitor to determine whether a CPU may rest based upon a...
US-6,847,929 Algebraic codebook system and method
Code-excited linear prediction speech encoders/decoders with excitation including an algebraic codebook contribution encoded with a single sign bit for each...
US-6,847,919 Characterizing an exposure tool for patterning a wafer
Characterizing an exposure tool involves receiving data describing a pattern formed at a wafer. The pattern is formed by illuminating the wafer using an exposure...
US-6,847,755 Optical cross connection switch using voltage-controlled interferometric optical switching elements
An optical switch comprising an array of voltage-controlled interferometric switching elements. Different configurations and modes of operation are possible, but...
US-6,847,754 Coordinated axis seeks with a micro-electro-mechanical mirror
A method of moving a MEM system mirror in a well defined trajectory that allows longer seeks to be used to reach a target position as compared with known methods...
US-6,847,593 Method for constructing compressed audio file system in a compact disc player
A method and apparatus for constructing a file tree in a compact disc player from the file system of a compressed audio CD is disclosed. After determining the...
US-6,847,321 Closed loop amplification with high throughput performance
Using an operational amplifier with a low gain in a closed loop amplifier circuit, and correcting for errors (i.e., deviation from the output of an ideal closed...
US-6,847,260 Low dropout monolithic linear regulator having wide operating load range
A monolithic low dropout regulator includes an active capacitor multiplier that is used to form the dominant pole of the regulator, thereby yielding stability....
US-6,847,235 Bus driver
An output driver includes a predriver circuit coupled to a complimentary MOS transistor pair. Third and fourth complimentary MOS transistors are coupled between...
US-6,847,232 Interchangeable CML/LVDS data transmission circuit
A system and method is described for a driver circuit used for high speed data transmission in LVDS and CML transceiver device applications. The transceivers are...
US-6,847,106 Semiconductor circuit with mechanically attached lid
One aspect of the invention is a semiconductor circuit comprising a semiconductor die electrically connected to a package substrate through a plurality of...
US-6,847,095 Variable reactor (varactor) with engineered capacitance-voltage characteristics
In one embodiment, a varactor includes a first node and a second node. The varactor includes: at least one first varactor element including a source, a drain,...
US-6,847,089 Gate edge diode leakage reduction
An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the...
US-6,847,080 Semiconductor device with high and low breakdown voltage and its manufacturing method
The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown...
US-6,846,217 Garment with interior bra structure with side supports
A women's garment with built-in breast support and no underwire, comprises an exterior fabric layer for covering the torso. A exterior fabric layer has an upper...
US-6,846,095 Lighted cassette alignment fixture
Disclosed is a lighted wafer cassette for use in semiconductor wafer processing. Also disclosed are systems and methods employing a wafer cassette lighted with...
US-6,844,775 Operational amplifier with adjustable input offset
An operational amplifier having an adjustable input offset is provided that can improve dynamic performance by allowing processing of the input signal in...
US-6,844,772 Threshold voltage extraction circuit
A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an...
US-6,844,760 LED drive circuit
A drive circuit for LEDs or other light-emitting elements with which the influence of the changes in temperature or power supply voltage and the element...
US-6,844,751 Multi-state test structures and methods
A test selector that multiplexes different test structures (202) to an adjacent probe pad (206) in dependence on the probe voltage. In addition, a scribeline...
US-6,844,566 Suspended gate single-electron device
The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (100) located over a substrate...
US-6,844,218 Semiconductor wafer with grouped integrated circuit die having inter-die connections for group testing
A method of forming a plurality of integrated circuit die on a semiconductor wafer (30). The method forms a first integrated circuit die (32.sub.a) in a first...
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