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Patent # Description
US-6,801,461 Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores...
US-6,801,116 Overload protector with hermetically sealing structure
Disclosed is an overload protector with a hermetically sealed structure, the overload protector comprising a housing that has an outer peripheral flange and an...
US-6,801,075 Method and circuit for base current compensation
A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a...
US-6,801,058 Circuit and method for over-current sensing and control
The present invention comprises a low side reverse recovery sense circuit (401) and a high side reverse recovery sense circuit (601), of a low side over-current...
US-6,801,057 Silicon-on-insulator dynamic logic
The SOI dynamic logic circuits comprises series and parallel pull-down networks (260) that comprise MOS transistors configured in series or parallel. Each pull...
US-6,800,944 Power/ground ring substrate for integrated circuits
A substrate (110) for an unpackaged integrated circuit (IC) chip (118). The substrate comprises an insulative material (112), a plurality of contacts (114)...
US-6,800,928 Porous integrated circuit dielectric with decreased surface porosity
A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling...
US-6,800,917 Bladed silicon-on-insulator semiconductor devices and method of making
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and...
US-6,800,555 Wire bonding process for copper-metallized integrated circuits
A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated...
US-6,800,547 Integrated circuit dielectric and method
A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling...
US-6,800,523 Integrated DRAM process/structure using contact pillars
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The...
US-6,799,266 Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as...
A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a...
US-6,799,136 Method of estimation of wafer polish rates
A method for extracting blanket (qual) polish rates from interferometry signals off patterned (product) wafer polish during non-enpointed CMP. The method...
US-6,799,134 Characterization of self-timed sequential circuits
A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting...
US-6,799,019 Method and system for accomodating processing delay in a cellular base station
A mobile telephone system and method having a base station for receiving data bursts during consecutive frames, each frame of predetermined time duration and...
US-6,798,737 Use of Walsh-Hadamard transform for forward link multiuser detection in CDMA systems
A station capable of receiving information containing Walsh coding for a plurality of channels and canceling interference from the received information and the...
US-6,798,591 Reference circuit for write driver circuit with programmable write current, overshoot duration and overshoot...
A write current circuit (40) adapted to drive a thin film write head (L0) of a mass media information storage device. The write current circuit includes a write...
US-6,798,521 Robust integrated surface plasmon resonance sensor
A surface plasmon resonance (SPR) sensor (10) is disclosed. The sensor (10) includes a light source (18) and polarizer (20), which emit polarized light toward a...
US-6,798,296 Wide band, wide operation range, general purpose digital phase locked loop architecture
A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and...
US-6,798,292 Highly linear low voltage rail-to-rail input/output operational amplifier
An operational amplifier circuit includes: a first differential pair 20 of a first conductivity type having a first current branch and a second current branch; a...
US-6,798,271 Clamping circuit and method for DMOS drivers
A transconductance circuit (16) and method for protecting an H-bridge power circuit (10) that provides power to a load that includes an inductive component (14)...
US-6,798,233 Digital method of measuring driver slew rates for reduced test time
A circuit (16,86) provides digital signals indicative of slew rates of phase signals (220) of H-bridge power drive transistors (60,62,64) of motor windings (66)...
US-6,798,212 Time domain reflectometer probe having a built-in reference ground point
A probe having a built-in reference plane for use with TDR testing includes a conductive sheet member such as a wire mesh which is attached to a ground input of...
US-6,797,935 Method of charging the photodiode element in active pixel arrays
A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and...
US-6,797,644 Method to reduce charge interface traps and channel hot carrier degradation
Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place...
US-6,797,633 In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
After via etch, a low-k dielectric layer (104) is treated with an in-situ O.sub.2 plasma. Resist poisoning is caused by a N source that causes an interaction...
US-6,797,599 Gate structure and method
A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate...
US-6,797,593 Methods and apparatus for improved mosfet drain extension activation
Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same...
US-6,797,577 One mask PNP (or NPN) transistor allowing high performance
A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost...
US-6,797,563 Method of forming cross point type DRAM cell
A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel...
US-6,797,547 Bladed silicon-on-insulator semiconductor devices and method of making
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and...
US-6,796,023 Method and apparatus for integrated circuit storage tube retention pin removal and insertion
While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still...
US-6,795,930 Microprocessor with selected partitions disabled during block repeat
A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of...
US-6,795,879 Apparatus and method for wait state analysis in a digital signal processing system
In order to analyze the conditions leading to a stall or a wait state in a digital signal processing unit, READY signals, that are typically applied to the...
US-6,795,548 Method and system for data communication
A system for data communication is disclosed that comprises a hybrid circuit (220) that receives a signal. A switched gain circuit (204) coupled to the hybrid...
US-6,795,283 Electricals package integrating run capacitor, motor protector and motor starter
A combination electricals package (12, 32) particularly for use with fractional horsepower compressor motors for various appliances has a first recess formed in...
US-6,795,265 Closed loop charge mode drive for piezo actuators using a DC restore amplifier
A piezo actuator drive circuit (40) adapted to operate in both a charge mode and a voltage mode. A low frequency compensation loop (44) is formed from a piezo...
US-6,795,264 LBA tracking for system data management
Systems and methodologies are disclosed for interfacing a storage medium with a host using a segmented buffer. Data blocks are transferred between the host and...
US-6,795,085 Contouring reduction in SLM-based display
Methods of reducing contouring in images display by a linear display device, such as a spatial light modulator. The methods operate on a high resolution signal,...
US-6,795,005 Variable, adaptive quantization in sigma-delta modulators
An improved sigma-delta modulation technique that may be employed in a sigma-delta Digital-to-Analog Converter (DAC) to convert digital signals into...
US-6,794,943 Ultra linear high speed operational amplifier output stage
The present invention provides an ultra linear, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage...
US-6,794,923 Low ripple charge pump for charging parasitic capacitances
A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The...
US-6,794,743 Structure and method of high performance two layer ball grid array substrate
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an...
US-6,794,738 Leadframe-to-plastic lock for IC package
Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the...
US-6,794,730 High performance PNP bipolar device fully compatible with CMOS process
A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the...
US-6,794,700 Capacitor having a dielectric layer including a group 17 element
The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the...
US-6,794,308 Method for reducing by-product deposition in wafer processing equipment
A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a...
US-6,794,252 Method and system for forming dual work function gate electrodes in a semiconductor device
A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly...
US-6,794,237 Lateral heterojunction bipolar transistor
A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20),...
US-6,794,235 Method of manufacturing a semiconductor device having a localized halo implant
The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an...
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