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Patent # Description
US-6,767,810 Method to increase substrate potential in MOS transistors used in ESD protection circuits
An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a...
US-6,767,777 Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching...
A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed...
US-6,767,750 Detection of AIOx ears for process control in FeRAM processing
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of...
US-6,766,487 Divided scan path with decode logic receiving select control signals
A low power scan architecture is formed of a conventional scan architecture. The conventional scan path is divided into equal parts and each part is operated in...
US-6,766,440 Microprocessor with conditional cross path stall to minimize CPU cycle time length
A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for...
US-6,766,421 Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having...
US-6,766,395 Extended common mode differential driver
A driver (300) which meets wide common mode voltage requirements is provided. Output passgates (310) protect sensitive line driver circuitry (305) from extreme...
US-6,766,338 High order lagrange sample rate conversion using tables for improved efficiency
A method for converting sample rates includes obtaining coefficients from a sample rate conversion coefficient table. In this method, the table is generated...
US-6,766,274 Determining the failure rate of an integrated circuit
The failure rate of an integrated circuit (IC) is quickly determined by analyzing the corresponding design. The IC is partitioned into multiple cells, with each...
US-6,765,980 Shift register
A shift register with low power consumption has memory circuits 15.sub.1 -15.sub.N connected in series, gate circuits in memory circuits 15.sub.2n-1 in the...
US-6,765,956 Multiple sampling frame synchronization in a wireline modem
A modem comprises circuitry for receiving an analog signal from a line and circuitry for converting the analog signal to a digital signal. The digital signal...
US-6,765,904 Packet networks
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,765,520 Method and circuit for jamming digital filter while resetting delta sigma modulator
An analog-to-digital converter (10) includes a high order delta sigma modulator followed by a decimation filter. A monitor circuit (104)coupled to the output of...
US-6,765,513 Decoding bit streams compressed with compression techniques employing variable length codes
A maximum length (M) of compressed codes desired to be decoded in a single lookup is determined. 2.sup.M rows are generated, with each row having a bit...
US-6,765,450 Common mode rejection in differential pairs using slotted ground planes
In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common...
US-6,765,391 Low cost asic architecture for safety critical applications monitoring an applied stimulus
An ASIC (14, 14', 14") conditions two independent outputs (VINM, VINP) of a full Wheatstone piezoresistive bridge (12) in separate conditioning paths. Each path...
US-6,765,257 Implanted vertical source-line under straight stack for flash eprom
In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical...
US-6,764,909 Structure and method of MOS transistor having increased substrate resistance
Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first...
US-6,764,892 Device and method of low voltage SCR protection for high voltage failsafe ESD applications
A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS...
US-6,764,872 Microelectromechanical switch
A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the...
US-6,764,795 Method and system for mask pattern correction
A method and system for mask pattern correction are disclosed. A portion of a mask pattern is segmented into segments (22) that include a base segment (22a) and...
US-6,763,724 Hermetic pressure transducer
A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal...
US-6,763,488 Generator/compactor scan circuit low power adapter with counter
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-6,763,487 IC with latching and switched I/O buffers
An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal thereof, which signal...
US-6,763,485 Position independent testing of circuits
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
US-6,763,450 Processor
The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP...
US-6,763,227 Systems and methods for modulator calibration
Systems and methods are provided for calibration of a transmitter system modulator, wherein local oscillator nodes of a mixer are held at first and second...
US-6,762,868 Electro-optical package with drop-in aperture
A drop-in aperture 20, which improves the performance and lowers the cost of electro-optical SLM packages. The disclosed package provides a separate metal light...
US-6,762,506 Assembly of semiconductor device and wiring substrate
Apparatus and method for assembling a semiconductor device on a wiring substrate is disclosed, wherein Pb (lead) is not used and the chance of generation of...
US-6,762,501 Low stress integrated circuit copper interconnect structures
Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110),...
US-6,762,498 Ball grid array package for high speed devices
A substrate (300) for use in semiconductor devices, having first (301a) and second (301b) surfaces and a base structure including insulating material. A...
US-6,762,130 Method of photolithographically forming extremely narrow transistor gate elements
A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is...
US-6,762,114 Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness
Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion...
US-6,760,866 Process of operating a processor with domains and clocks
A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry...
US-6,760,837 Bit field processor
An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also...
US-6,760,829 MMU descriptor having big/little endian bit to control the transfer data between devices
A digital system is provided with a memory (506) shared by several initiator resources (540-550), wherein a portion of the initiator resources are big endian and...
US-6,760,802 Time-out counter for multiple transaction bus system bus bridge
The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt on reads from a second bus...
US-6,760,742 Multi-dimensional galois field multiplier
An implementation of a multi-dimensional Galois field multiplier and a method of Galois field multi-dimensional multiplication which are able to support many...
US-6,760,333 Hybrid digital subscriber loop and voice-band universal serial bus modem
A Universal Serial Bus (USB) modem (14) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB...
US-6,760,247 Methods and apparatus for flexible memory access
Memory devices and methods are presented for selectively reading or writing rows or columns of memory cells in a ferroelectric memory array, wherein sense amps...
US-6,760,173 Synchronization servo mark detector and method having improved phase error immunity for use in mass data...
A detector (55) and method for detecting a synchronization servo mark (SSM) in a data stream of mass data storage device (10) has a matched filter (56) to...
US-6,759,892 Temperature compensation trim method
The present invention overcomes the disadvantages of the prior art and provides a new temperature compensation trimming technique. Temperature compensated output...
US-6,759,745 Semiconductor device and manufacturing method thereof
A type of semiconductor device and its manufacturing method, which can further miniaturize semiconductor devices and reduce design restrictions by minimizing the...
US-6,759,278 Method for surface mounted power transistor with heat sink
A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on...
US-6,758,571 Scanning MEMS mirror with reluctance force motor
A movable mirror device driven by a reluctance force motor is provided. A sheet of material has a mirror portion, a hinge portion, and a frame portion formed...
US-6,757,829 Program debugging system for secure computing device having secure and non-secure modes
The method of secure computing concerns the security of a debugger/emulator tool commonly employed in program development. A private encryption key is used to...
US-6,757,819 Microprocessor with instructions for shifting data responsive to a signed count value
A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count...
US-6,757,775 Batch method for accessing IDE device task registers
The method maps at least one intermediate data register of a first data width into the address space of the computer bus. The computer bus writes data to an...
US-6,757,396 Digital audio dynamic range compressor and method
A digital audio dynamic range compressor includes a root mean square estimator receiving first and second audio input samples and generating root mean square...
US-6,757,256 Process of sending packets of real-time information
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
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