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Patent # Description
US-6,774,031 Method of forming dual-damascene structure
A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second...
US-6,773,972 Memory cell with transistors having relatively high threshold voltages in response to selective gate doping
A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region...
US-6,773,930 Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer...
US-6,773,617 Method and apparatus for restricting process fluid flow within a showerhead assembly
A system and method are disclosed for restricting process fluid flow within a showerhead assembly which includes a process chamber (12) with a showerhead...
US-6,772,377 Convolutional interleaving with interleave depth larger than codeword size
The present invention provides a solution for interleaving data frames, in a digital subscriber line system in which the data frames are divided into first and...
US-6,772,326 Interruptible an re-entrant cache clean range instruction
A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start...
US-6,772,311 ATAPI device unaligned and aligned parallel I/O data transfer controller
A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve...
US-6,771,894 Motor control resolution enhancement
A motor speed resolution enhancement method and system. A display system controller (202) measures the frame rate of an incoming signal to determine the desired...
US-6,771,691 System and method for extracting soft symbols in direct sequence spread spectrum communications
An integrated circuit including a demodulating finger is provided for variably extracting symbols in the demodulation process of spread spectrum signals....
US-6,771,480 Circuit to sample and compare the BEMF on an actuator into a constant velocity control
A apparatus for controlling an actuator including, an integrator circuit to generate an integrated signal to be represented by a back EMF voltage, a amount...
US-6,771,371 Particle detection and removal apparatus for use on wafer fabrication equipment to lower tool related defects...
A portable particle detection and removal system (100) that connects to a house vacuum (200). A particle sensor (106) is connected between two hoses: one (102)...
US-6,771,325 Color recapture for display systems
A sequential color display system using a white light source (202) to create a full color image projected onto an image plane (214). A dynamic filter (206),...
US-6,771,252 Shading of inequalities on a graphing calculator
A graphing calculator (10) or other computer based teaching tool that displays inequalities on a display screen. In contrast to prior art devices, the present...
US-6,771,118 System and method for reducing a leakage current associated with an integrated circuit
A method for reducing a leakage current in an integrated circuit is provided that includes controlling one or more inputs of an integrated circuit such that one...
US-6,771,106 Programmable delay for processor control signals
A programmable delay circuit (100) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only way for satisfying timing...
US-6,770,952 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices
High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28)...
US-6,770,937 Photoconductive thin film for reduction of plasma damage
A semiconductor device (200) that includes a semiconductor substrate (210), semiconductor features (230, 235, 240, 260) located thereover and an insulating...
US-6,770,935 Array of transistors with low voltage collector protection
An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain...
US-6,770,933 Single poly eeprom with improved coupling ratio
A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well...
US-6,770,521 Method of making multiple work function gates by implanting metals with metallic alloying additives
A method of forming a first and second transistors with differing work function gates by differing metals with a second metal selectively implanted or diffused...
US-6,769,080 Scan circuit low power adapter with counter
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-6,769,052 Cache with selective write allocation
A digital system and method of operation is provided in which several processors (590n) are connected to a shared cache memory resource (500). A translation...
US-6,768,977 Method and circuit for modeling a voice coil actuator of a mass data storage device
A circuit model (50) for use in analyzing a VCM circuit has a first resistor (62), a first inductor (64), a second inductor (58), and a voltage source (60), in...
US-6,768,951 Apparatus and method for measuring a parameter in a host device
An apparatus receives an indicating signal representing a parameter at a monitoring locus and includes: (a) A first measuring unit having a first input coupled...
US-6,768,669 Volatile memory cell reconfigured as a non-volatile memory cell
A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but...
US-6,768,663 Semiconductor device array having dense memory cell array and hierarchical bit line scheme
A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments...
US-6,768,646 High density internal ball grid array integrated circuit package
An integrated circuit package (30) comprising a substrate (70) having peripheral openings (86) and first and second surfaces (92, 94), a plurality of routing...
US-6,768,623 IC excess current detection scheme
The present invention achieves technical advantages as a circuit (10) detecting excess current on a servo driver IC and preventing the disruptive damage which...
US-6,768,436 Method and circuit resetting delta sigma modulator
A delta sigma modulator circuit sums an input signal with a feedback signal representing signal conditions in a group of integrators to provide an input to a...
US-6,768,318 Signal conditioning circuit for resistive sensors
A circuit is provided that can provide, in a single package, a circuit to monitor a sensing element which uses a variable resistor. The circuit (also known as a...
US-6,768,288 Circuit for detecting low battery condition on an electronic device with a changing load
A method to more accurately monitor remaining battery life under varying load conditions. The measured battery voltage is adjusted for the current load and then...
US-6,768,212 Semiconductor packages and methods for manufacturing such semiconductor packages
A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for...
US-6,768,210 Bumpless wafer scale device and board assembly
A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact...
US-6,768,144 Method and apparatus for reducing leakage current in an SRAM array
A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a...
US-6,767,810 Method to increase substrate potential in MOS transistors used in ESD protection circuits
An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a...
US-6,767,777 Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching...
A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed...
US-6,767,750 Detection of AIOx ears for process control in FeRAM processing
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of...
US-6,766,487 Divided scan path with decode logic receiving select control signals
A low power scan architecture is formed of a conventional scan architecture. The conventional scan path is divided into equal parts and each part is operated in...
US-6,766,440 Microprocessor with conditional cross path stall to minimize CPU cycle time length
A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for...
US-6,766,421 Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having...
US-6,766,395 Extended common mode differential driver
A driver (300) which meets wide common mode voltage requirements is provided. Output passgates (310) protect sensitive line driver circuitry (305) from extreme...
US-6,766,338 High order lagrange sample rate conversion using tables for improved efficiency
A method for converting sample rates includes obtaining coefficients from a sample rate conversion coefficient table. In this method, the table is generated...
US-6,766,274 Determining the failure rate of an integrated circuit
The failure rate of an integrated circuit (IC) is quickly determined by analyzing the corresponding design. The IC is partitioned into multiple cells, with each...
US-6,765,980 Shift register
A shift register with low power consumption has memory circuits 15.sub.1 -15.sub.N connected in series, gate circuits in memory circuits 15.sub.2n-1 in the...
US-6,765,956 Multiple sampling frame synchronization in a wireline modem
A modem comprises circuitry for receiving an analog signal from a line and circuitry for converting the analog signal to a digital signal. The digital signal...
US-6,765,904 Packet networks
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,765,520 Method and circuit for jamming digital filter while resetting delta sigma modulator
An analog-to-digital converter (10) includes a high order delta sigma modulator followed by a decimation filter. A monitor circuit (104)coupled to the output of...
US-6,765,513 Decoding bit streams compressed with compression techniques employing variable length codes
A maximum length (M) of compressed codes desired to be decoded in a single lookup is determined. 2.sup.M rows are generated, with each row having a bit...
US-6,765,450 Common mode rejection in differential pairs using slotted ground planes
In high-speed semiconductor packaging, differential pair transmission lines 605 are used to receive incoming signals carried using differential signaling. Common...
US-6,765,391 Low cost asic architecture for safety critical applications monitoring an applied stimulus
An ASIC (14, 14', 14") conditions two independent outputs (VINM, VINP) of a full Wheatstone piezoresistive bridge (12) in separate conditioning paths. Each path...
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