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Patent # Description
US-6,804,243 Hardware acceleration for segmentation of message packets in a universal serial bus peripheral device
A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB...
US-6,804,141 Dynamic reference voltage calibration integrated FeRAMS
A FeRAM includes a reference voltage calibration circuit that evaluates FeRAM cells and selects reference voltages for reading the FeRAM cells. Calibration of...
US-6,804,095 Drain-extended MOS ESD protection structure
A protection structure (30; 30'; 30") for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure...
US-6,803,938 Dynamic laser printer scanning alignment using a torsional hinge mirror
In a laser printer which uses a scanning mirror 12 with torsional hinges 36A, 36B driven by electrical coils 30A, 30B to provide resonant pivoting, at least one...
US-6,803,830 Phase-locked loop and method for automatically setting its output frequency
A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a...
US-6,803,811 Active hybrid circuit
A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a...
US-6,803,661 Polysilicon processing using an anti-reflective dual layer hardmask for 193 nm lithography
A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an...
US-6,803,641 MIM capacitors and methods for fabricating same
Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling...
US-6,803,611 Use of indium to define work function of p-type doped polysilicon
The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate...
US-6,803,295 Versatile system for limiting mobile charge ingress in SOI semiconductor structures
Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the...
US-6,803,282 Methods for fabricating low CHC degradation mosfet transistors
Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions...
US-6,803,273 Method to salicide source-line in flash memory with STI
A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming...
US-6,802,987 Integrated circuit ferroelectric infrared detector and method
Ferroelectric materials useful in monolithic uncooled infrared imaging use Ca and Sn substitutions in PbTiO3 and also have alternatives with dopants such as Dy,...
US-6,802,119 Conductive pedestal on pad for leadless chip carrier (LCC) standoff
A device and method for insuring the separation between a leadless chip carrier and printed wiring board, comprising aligning and attaching conductive pedestals...
US-6,801,985 Data bus using synchronous fixed latency loop including read address and data busses and write address and data...
Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus...
US-6,801,958 Method and system for data transfer
According to one embodiment of the present invention, a system (10) for data transfer is disclosed that comprises a transfer memory (24) having one or more...
US-6,801,922 Sampling rate converter and method
Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated...
US-6,801,588 Combined channel and entropy decoding
A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional...
US-6,801,567 Frequency bin method of initial carrier frequency acquisition
A frequency bin method of carrier frequency acquisition uses a plurality of predetermined carrier frequency offset bins. A single bin is selected from among the...
US-6,801,532 Packet reconstruction processes for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,801,499 Diversity schemes for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,801,461 Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores...
US-6,801,116 Overload protector with hermetically sealing structure
Disclosed is an overload protector with a hermetically sealed structure, the overload protector comprising a housing that has an outer peripheral flange and an...
US-6,801,075 Method and circuit for base current compensation
A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a...
US-6,801,058 Circuit and method for over-current sensing and control
The present invention comprises a low side reverse recovery sense circuit (401) and a high side reverse recovery sense circuit (601), of a low side over-current...
US-6,801,057 Silicon-on-insulator dynamic logic
The SOI dynamic logic circuits comprises series and parallel pull-down networks (260) that comprise MOS transistors configured in series or parallel. Each pull...
US-6,800,944 Power/ground ring substrate for integrated circuits
A substrate (110) for an unpackaged integrated circuit (IC) chip (118). The substrate comprises an insulative material (112), a plurality of contacts (114)...
US-6,800,928 Porous integrated circuit dielectric with decreased surface porosity
A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling...
US-6,800,917 Bladed silicon-on-insulator semiconductor devices and method of making
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and...
US-6,800,555 Wire bonding process for copper-metallized integrated circuits
A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated...
US-6,800,547 Integrated circuit dielectric and method
A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling...
US-6,800,523 Integrated DRAM process/structure using contact pillars
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The...
US-6,799,266 Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as...
A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a...
US-6,799,136 Method of estimation of wafer polish rates
A method for extracting blanket (qual) polish rates from interferometry signals off patterned (product) wafer polish during non-enpointed CMP. The method...
US-6,799,134 Characterization of self-timed sequential circuits
A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting...
US-6,799,019 Method and system for accomodating processing delay in a cellular base station
A mobile telephone system and method having a base station for receiving data bursts during consecutive frames, each frame of predetermined time duration and...
US-6,798,737 Use of Walsh-Hadamard transform for forward link multiuser detection in CDMA systems
A station capable of receiving information containing Walsh coding for a plurality of channels and canceling interference from the received information and the...
US-6,798,591 Reference circuit for write driver circuit with programmable write current, overshoot duration and overshoot...
A write current circuit (40) adapted to drive a thin film write head (L0) of a mass media information storage device. The write current circuit includes a write...
US-6,798,521 Robust integrated surface plasmon resonance sensor
A surface plasmon resonance (SPR) sensor (10) is disclosed. The sensor (10) includes a light source (18) and polarizer (20), which emit polarized light toward a...
US-6,798,296 Wide band, wide operation range, general purpose digital phase locked loop architecture
A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and...
US-6,798,292 Highly linear low voltage rail-to-rail input/output operational amplifier
An operational amplifier circuit includes: a first differential pair 20 of a first conductivity type having a first current branch and a second current branch; a...
US-6,798,271 Clamping circuit and method for DMOS drivers
A transconductance circuit (16) and method for protecting an H-bridge power circuit (10) that provides power to a load that includes an inductive component (14)...
US-6,798,233 Digital method of measuring driver slew rates for reduced test time
A circuit (16,86) provides digital signals indicative of slew rates of phase signals (220) of H-bridge power drive transistors (60,62,64) of motor windings (66)...
US-6,798,212 Time domain reflectometer probe having a built-in reference ground point
A probe having a built-in reference plane for use with TDR testing includes a conductive sheet member such as a wire mesh which is attached to a ground input of...
US-6,797,935 Method of charging the photodiode element in active pixel arrays
A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and...
US-6,797,644 Method to reduce charge interface traps and channel hot carrier degradation
Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place...
US-6,797,633 In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
After via etch, a low-k dielectric layer (104) is treated with an in-situ O.sub.2 plasma. Resist poisoning is caused by a N source that causes an interaction...
US-6,797,599 Gate structure and method
A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate...
US-6,797,593 Methods and apparatus for improved mosfet drain extension activation
Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same...
US-6,797,577 One mask PNP (or NPN) transistor allowing high performance
A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost...
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