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Patent # Description
US-6,797,563 Method of forming cross point type DRAM cell
A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel...
US-6,797,547 Bladed silicon-on-insulator semiconductor devices and method of making
A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and...
US-6,796,023 Method and apparatus for integrated circuit storage tube retention pin removal and insertion
While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still...
US-6,795,930 Microprocessor with selected partitions disabled during block repeat
A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of...
US-6,795,879 Apparatus and method for wait state analysis in a digital signal processing system
In order to analyze the conditions leading to a stall or a wait state in a digital signal processing unit, READY signals, that are typically applied to the...
US-6,795,548 Method and system for data communication
A system for data communication is disclosed that comprises a hybrid circuit (220) that receives a signal. A switched gain circuit (204) coupled to the hybrid...
US-6,795,283 Electricals package integrating run capacitor, motor protector and motor starter
A combination electricals package (12, 32) particularly for use with fractional horsepower compressor motors for various appliances has a first recess formed in...
US-6,795,265 Closed loop charge mode drive for piezo actuators using a DC restore amplifier
A piezo actuator drive circuit (40) adapted to operate in both a charge mode and a voltage mode. A low frequency compensation loop (44) is formed from a piezo...
US-6,795,264 LBA tracking for system data management
Systems and methodologies are disclosed for interfacing a storage medium with a host using a segmented buffer. Data blocks are transferred between the host and...
US-6,795,085 Contouring reduction in SLM-based display
Methods of reducing contouring in images display by a linear display device, such as a spatial light modulator. The methods operate on a high resolution signal,...
US-6,795,005 Variable, adaptive quantization in sigma-delta modulators
An improved sigma-delta modulation technique that may be employed in a sigma-delta Digital-to-Analog Converter (DAC) to convert digital signals into...
US-6,794,943 Ultra linear high speed operational amplifier output stage
The present invention provides an ultra linear, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage...
US-6,794,923 Low ripple charge pump for charging parasitic capacitances
A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The...
US-6,794,743 Structure and method of high performance two layer ball grid array substrate
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an...
US-6,794,738 Leadframe-to-plastic lock for IC package
Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the...
US-6,794,730 High performance PNP bipolar device fully compatible with CMOS process
A pnp bipolar junction transistor is formed with improved emitter efficiency by reducing the depth of the p well implant to increase carrier concentration in the...
US-6,794,700 Capacitor having a dielectric layer including a group 17 element
The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the...
US-6,794,308 Method for reducing by-product deposition in wafer processing equipment
A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a...
US-6,794,252 Method and system for forming dual work function gate electrodes in a semiconductor device
A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly...
US-6,794,237 Lateral heterojunction bipolar transistor
A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20),...
US-6,794,235 Method of manufacturing a semiconductor device having a localized halo implant
The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an...
US-6,792,508 Cache with multiple fill modes
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be...
US-6,792,386 Method and system for statistical comparison of a plurality of testers
The invention provides methods and systems for statistically comparing yields among two or more testers in a testing environment where a lot of manufactured...
US-6,792,054 Method for reducing complex frequency down-conversion impairments
An improved receiver is provided having a voltage controlled amplifier for adjusting the gain of a first input signal, a comparator and integrator for...
US-6,792,031 Method for maintaining timing in a CDMA rake receiver
A system and method for maintaining timing in a CDMA rake receiver has a global chip counter that counts CDMA signal chips as they arrive at the CDMA rake...
US-6,792,019 Driver with tail currents in discrete subranges
The laser driver circuit includes an array of differential pairs 50 and 52. Each one of the differential pairs is coupled to a corresponding tail current source...
US-6,791,864 Column voltage control for write
A memory device including array (12) of memory cells (10) having an array voltage Vdd bussed such that the Vdd of columns are controlled independently. During a...
US-6,791,609 Digital still camera system and method
A combination interpolation and lowpass filtering for Bayer color-filtered arrays with the green high frequency used as an estimate for red and blue high frequency.
US-6,791,607 Optical black and offset correction in CCD signal processing
An image processing apparatus for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the an offset...
US-6,791,526 Drive circuit
A drive circuit, for example a gate line drive circuit for a TFT liquid-crystal display, having a circuit size smaller than in the past. A TFT drive circuit has...
US-6,791,422 Frequency synthesizer with digitally-controlled oscillator
A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC...
US-6,791,383 Reduced gate leakage current in thin gate dielectric CMOS integrated circuits
The invention describes a method for reducing the leakage current in thin gate dielectric MOS capacitors in integrated circuits. A bias voltage is determined for...
US-6,791,365 Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage...
A dynamic logic circuit (30). The dynamic logic circuit comprises a precharge node (30.sub.PN) to be precharged to a precharge voltage (V.sub.DD) during a...
US-6,791,312 Measuring power of analog signals
An original rectifier circuit is used to rectify an input signal and the input signal is coupled to be provided to a terminal of a amplifier. The amplifier is...
US-6,790,777 Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device
The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate...
US-6,790,736 Method for manufacturing and structure of semiconductor device with polysilicon definition structure
In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a...
US-6,789,240 Method of controlling bond process quality by measuring wire bond features
A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond...
US-6,789,238 System and method to improve IC fabrication through selective fusing
A system and methodology for fabricating integrated circuits (ICs) on wafer die monitors at a subset of die one or more parameters that can affect the ...
US-6,789,183 Apparatus and method for activation of a digital signal processor in an idle mode for interprocessor transfer...
In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group...
US-6,789,172 Cache and DMA with a global valid bit
A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the...
US-6,789,031 Method for determining the equivalency index of products, processes, and services
A method is disclosed wherewith a person skilled in the art of statistical quality control may determine whether a process, a product or a service is statically...
US-6,789,026 Circuit and method for monitoring battery state of charge
A processor (13) operates to determine amount of charge presently stored in a battery by determining that the battery is in a zero-current relaxed condition....
US-6,788,469 Automated lamp focus
Methods for measuring and automatically controlling the light distribution and overall brightness in electronic-based spatial light modulator projection display...
US-6,788,416 Method and apparatus for dynamic DMD testing
A method and apparatus for measuring the transient behavior characteristics of individual micromirrors in a DMD micromirror array. The method and system use...
US-6,788,340 Digital imaging control with selective intensity resolution enhancement
Image enhancement is automatically achieved by calibrating the reference voltage and gain of a differential amplifier and the integration interval so as to...
US-6,788,160 Oscillator circuit connected to a voltage source providing a substantially constant supply voltage
The invention relates to a voltage-controlled oscillator circuit including an oscillator circuit connected to a voltage source furnishing a substantially...
US-6,788,146 Capacitor compensation in miller compensated circuits
A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A...
US-6,788,144 Variable-gain amplifier
A variable-gain amplifier that prevents the change in the in-phase voltage of the output occurring when the gain is changed and improves the frequency...
US-6,788,140 Ultra-low distortion, wide-bandwidth amplifier architecture using actively phase-matched feed-forward linearization
An amplifier architecture using actively phase-matched feed-forward linearization includes: a first signal path having a scaling amplifier 40 in series with a...
US-6,788,130 Efficient charge pump capable of high voltage operation
A high voltage integrated circuit operable in a system having a low voltage reference, a high voltage reference, and a ground, for providing an output voltage...
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