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Patent # Description
US-6,746,886 MEMS device with controlled gas space chemistry
A process for protecting a MEMS device used in a UV illuminated application from damage due to a photochemical activation between the UV flux and package gas...
US-6,745,319 Microprocessor with instructions for shuffling and dealing data
A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the...
US-6,745,293 Level 2 smartcache architecture supporting simultaneous multiprocessor accesses
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having...
US-6,744,757 Private branch exchange systems for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,744,533 Efficient buffer rendering
A method and system for efficient buffer rendering. An object mask, typically a character font mask, is aligned with a memory tiling arrangement (1102). A tile...
US-6,744,280 Voltage output differential (VOD) correction circuit for differential drivers
System and methods are provided for monitoring circuit performance and correcting for variations in current reference signals to maintain a desired Voltage...
US-6,744,243 System and method for dynamically regulating a step down power supply
A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the...
US-6,744,034 Micro-electromechanical apparatus and method with position sensor compensation
Micro-electromechanical apparatus and method with position sensor compensation to compensate for sensor drift. A preferred embodiment comprises modifying the...
US-6,743,719 Method for forming a conductive copper structure
The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of...
US-6,743,705 Transistor with improved source/drain extension dopant concentration
A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in...
US-6,743,684 Method to produce localized halo for MOS transistor
Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a...
US-6,743,656 MEMS wafer level package
An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer...
US-6,742,395 Hermetic pressure transducer
A port fitting (102) is formed with a closed, pedestal end forming a diaphragm (102a) on which a strain gauge sensor is mounted. A support member (106) is...
US-6,742,110 Preventing the execution of a set of instructions in parallel based on an indication that the instructions were...
A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first...
US-6,742,104 Master/slave processing system with shared translation lookaside buffer
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide...
US-6,742,103 Processing system with shared translation lookaside buffer
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide...
US-6,742,058 Memory controller having a multiplexer selecting either second set of input signals or converted signals from...
A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The...
US-6,741,750 Motion artifact correction in exposure systems
A system and method for correcting spatial banding artifacts in print images. The system includes: a light source, a spatial light modulator, a transport system...
US-6,741,611 Packet memory management (PACMAN) scheme
The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of...
US-6,741,503 SLM display data address mapping for four bank frame buffer
A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into...
US-6,741,333 Multiple image photolithography system and method
A multiple image photolithography system includes a radiation source (18) projecting electromagnetic radiation along a path. A reticle cartridge (26) is located...
US-6,741,129 Differential amplifier slew rate boosting scheme
A fully differential amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain very near unity or less has the first plates of the...
US-6,741,098 High speed semiconductor circuit having low power consumption
A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power...
US-6,741,088 Semiconductor testing device having a nest with a detachable anvil
A semiconductor testing device having a nest for holding an integrated circuit during testing. The nest comprises a plate having a front side and a back side, a...
US-6,740,905 Apparatus for suppressing crosstalk in image sensors without degrading red light response
The image sensor has improvements for suppressing cross talk without degrading red light response. This is accomplished by implanting a deep p+ layer 42 under...
US-6,740,603 Control of Vmin transient voltage drift by maintaining a temperature less than or equal to 350.degree. C. after...
A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top...
US-6,738,964 Graphical development system and method
A graphical solutions development system using placement of blocks representing hardware/software functionality on a computer screen drawing and connecting the...
US-6,738,929 Dynamically configurable debug port for concurrent support of debug functions from multiple data processing cores
An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity...
US-6,738,888 TLB with resource ID field
A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation...
US-6,738,881 Multi-channel DMA with scheduled ports
A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source...
US-6,738,864 Level 2 cache architecture for multiprocessor with task--ID and resource--ID
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having...
US-6,738,860 Synchronous DRAM with control data buffer
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,738,206 Decision error compensation technique for decision-directed timing recovery loop
A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining...
US-6,738,104 Robust color wheel phase error method for improved channel change re-lock performance
A new method for phase locking the color wheel in a color field-sequential projection display. At periodic interrupts, the method determines which color wheel...
US-6,738,074 Image compression system and method
A method for generating image compression quantization matrices is disclosed. A method includes a step of locating a frequency coefficient (120) within a...
US-6,738,048 Touch screen controller
An improved touch screen controller including a comparator and an analog-to-digital converter. The comparator of the touch screen controller detects a touch of...
US-6,737,952 Combined pressure responsive electrical switch and temperature sensor device
A combined pressure responsive electrical switch and temperature sensor device (10, 10') is shown comprising a base member (12) mounting an electrical switch...
US-6,737,848 Reference voltage source
The invention relates to a reference voltage source including a bipolar transistor having a base, a collector and an emitter electrode. The reference voltage...
US-6,737,354 Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates
An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that...
US-6,737,351 Versatile system for diffusion limiting void formation
Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device...
US-6,737,347 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain...
US-6,737,333 Semiconductor device isolation structure and method of forming
A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer...
US-6,737,326 Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect
A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and...
US-6,737,325 Method and system for forming a transistor having source and drain extensions
According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a...
US-6,737,225 Method of undercutting micro-mechanical device with super-critical carbon dioxide
A method for removing sacrificial layers during the process of fabricating micro-mechanical devices with a solution of super-critical carbon dioxide. A mixture...
US-6,736,521 On axis translational motion stops for movable structure having torsional hinge
A device 21 comprises a movable structure 44 having a first movable portion 70 hinged to frame portion 60 by a first pair of hinges 81, 82 spaced apart along a...
US-6,735,737 Error correction structures and methods
A parallel Chien search by partitioning of the nonzero elements of a root field and using a parallel Galois multiplier.
US-6,735,724 Detection error estimation and method
A method of monitoring the performance of a Viterbi detector by using the deviations from the noiseless case of the path difference of the two branches entering...
US-6,735,668 Process of using a DRAM with address control data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,735,667 Synchronous data system with control data buffer
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
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