Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: texas instruments





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-6,731,564 Method and system for power conservation in memory devices
According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a...
US-6,731,533 Loadless 4T SRAM cell with PMOS drivers
The instant invention comprises a memory cell with PMOS drive transistors (170, 180) and NMOS pass transistors (150, 160). A NMOS transistor is connected between...
US-6,731,420 Optical switching apparatus
An optical matrix switch station (1) is shown mounting a plurality of optical switch units (15, 17), each of which includes a mirror (29), moveable in two axes,...
US-6,731,406 Segmented multilevel screening for printing files in a page description language
This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time...
US-6,731,163 Miller de-compensation for differential input, differential output amplifier
A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential...
US-6,731,132 Programmable line terminator
A programmable line terminator device that can optimally terminate a transmission line or bus even if the line impedance is variable or not well defined. The...
US-6,731,127 Parallel integrated circuit test apparatus and test method
A test apparatus (300) comprising a single handler (304) is coupled to a first tester (336) and second tester (308). A first test procedure is performed on a set...
US-6,731,106 Measuring on-resistance of an output buffer with test terminals
The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary...
US-6,730,977 Lower temperature method for forming high quality silicon-nitrogen dielectrics
A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick...
US-6,730,962 Method of manufacturing and structure of semiconductor device with field oxide structure
A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of...
US-6,730,950 Local interconnect using the electrode of a ferroelectric
Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The...
US-6,730,616 Versatile plasma processing system for producing oxidation resistant barriers
A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and...
US-6,730,613 Method for reducing by-product deposition in wafer processing equipment
A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a...
US-6,730,597 Pre-ECD wet surface modification to improve wettability and reduced void defect
A pre-ECD wet surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with a water-based...
US-6,730,582 Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD)...
A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G.sub.2) in a fixed relationship to the ...
US-6,730,569 Field effect transistor with improved isolation structures
An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and...
US-6,730,566 Method for non-thermally nitrided gate formation for high voltage devices
A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the...
US-6,730,556 Complementary transistors with controlled drain extension overlap
An integrated circuit device (60) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type...
US-6,730,555 Transistors having selectively doped channel regions
An integrated semiconductor system is provided that is formed on a substrate 10. A dual implant mask 26 is used to change the characteristics of semiconductor...
US-6,730,554 Multi-layer silicide block process
An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125)...
US-6,730,541 Wafer-scale assembly of chip-size packages
A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a...
US-6,730,354 Forming ferroelectric Pb(Zr,Ti)O3 films
Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These...
US-6,729,947 Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
US-6,729,886 Method of fabricating a drain isolated LDMOS device
A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a...
US-6,728,950 Method and apparatus for translating between source and target code
An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source...
US-6,728,928 Modified viterbi detector for jitter noise dominant channels
A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to .lambda..sub.k.sup.(i)...
US-6,728,915 IC with shared scan cells selectively connected in scan path
This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in...
US-6,728,838 Cache operation based on range of addresses
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory...
US-6,728,829 Synchronous DRAM system with control data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,728,828 Synchronous data transfer system
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,728,741 Hardware assist for data block diagonal mirror image transformation
A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises...
US-6,728,320 Capacitive data and clock transmission between isolated ICs
A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first...
US-6,728,302 STTD encoding for PCCPCH
A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a...
US-6,728,301 System and method for automatic frequency control in spread spectrum communications
A method is providing for calculating local oscillator phase errors in a code division multiple access (CDMA) receiver using an arctangent calculation of the...
US-6,728,128 Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device...
US-6,728,056 Current stealing circuit to control the impedance of a TGMR head amplifier biasing circuit regardless of...
An impedance controlling circuit (152) is connected across an MR head (42) and has two current paths, each including a control transistor (154,156), a current...
US-6,727,757 Biasing circuit for transconductors
A transconductor circuit, including a differential transconductor amplifier circuit. The transconductor circuit includes an input pair of transistors adapted to...
US-6,727,755 High speed linear variable gain amplifier architecture
A two stage amplifier circuit (10), the first stage (12) comprising a modified quad configuration and the second stage (14) comprising a translinear current...
US-6,727,752 Modulation scheme for switching amplifiers to reduce filtering requirements and crossover distortion
A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a...
US-6,727,722 Process of testing a semiconductor wafer of IC dies
Integrated circuit die on a wafer are tested individually, without probing any of the die, using circuitry (TC1-8, BC1-8, LR1-8, RR1-8, PA1-PA4) provided on the...
US-6,727,578 Semiconductor device having power supply voltage routed through substrate
A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped...
US-6,727,185 Dry process for post oxide etch residue removal
A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues (116).
US-6,727,133 Integrated circuit resistors in a high performance CMOS process
An integrated circuit resistor (150) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (74)...
US-6,727,131 System and method for addressing junction capacitances in semiconductor devices
A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a...
US-6,725,409 DSP instruction for turbo decoding
The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor....
US-6,725,391 Clock modes for a debug port with on the fly clock switching
An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a...
US-6,725,202 Transaction accounting of toll transactions in transponder systems
This invention allows a toll authority to monitor transaction numbers which are sent from a transponder (14) to an interrogator (12). By incrementing the...
US-6,725,025 Interference cancellation among wireless units using Gibbs sampling
An improved interference cancellation technique is disclosed. Digital baseband circuitry (40) includes user and symbol detection circuitry (50) for performing a...
US-6,724,828 Mobile switching between STTD and non-diversity mode
A communication circuit is designed with a detector circuit (720) coupled to receive a first signal. The detector circuit is arranged to produce a multipath...
US-6,724,646 Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.