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Patent # Description
US-6,741,333 Multiple image photolithography system and method
A multiple image photolithography system includes a radiation source (18) projecting electromagnetic radiation along a path. A reticle cartridge (26) is located...
US-6,741,129 Differential amplifier slew rate boosting scheme
A fully differential amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain very near unity or less has the first plates of the...
US-6,741,098 High speed semiconductor circuit having low power consumption
A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power...
US-6,741,088 Semiconductor testing device having a nest with a detachable anvil
A semiconductor testing device having a nest for holding an integrated circuit during testing. The nest comprises a plate having a front side and a back side, a...
US-6,740,905 Apparatus for suppressing crosstalk in image sensors without degrading red light response
The image sensor has improvements for suppressing cross talk without degrading red light response. This is accomplished by implanting a deep p+ layer 42 under...
US-6,740,603 Control of Vmin transient voltage drift by maintaining a temperature less than or equal to 350.degree. C. after...
A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top...
US-6,738,964 Graphical development system and method
A graphical solutions development system using placement of blocks representing hardware/software functionality on a computer screen drawing and connecting the...
US-6,738,929 Dynamically configurable debug port for concurrent support of debug functions from multiple data processing cores
An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity...
US-6,738,888 TLB with resource ID field
A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation...
US-6,738,881 Multi-channel DMA with scheduled ports
A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source...
US-6,738,864 Level 2 cache architecture for multiprocessor with task--ID and resource--ID
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having...
US-6,738,860 Synchronous DRAM with control data buffer
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,738,206 Decision error compensation technique for decision-directed timing recovery loop
A circuit for use in a phase lock loop including a first phase detector to detect a first phase error between input signals, the first phase detector obtaining...
US-6,738,104 Robust color wheel phase error method for improved channel change re-lock performance
A new method for phase locking the color wheel in a color field-sequential projection display. At periodic interrupts, the method determines which color wheel...
US-6,738,074 Image compression system and method
A method for generating image compression quantization matrices is disclosed. A method includes a step of locating a frequency coefficient (120) within a...
US-6,738,048 Touch screen controller
An improved touch screen controller including a comparator and an analog-to-digital converter. The comparator of the touch screen controller detects a touch of...
US-6,737,952 Combined pressure responsive electrical switch and temperature sensor device
A combined pressure responsive electrical switch and temperature sensor device (10, 10') is shown comprising a base member (12) mounting an electrical switch...
US-6,737,848 Reference voltage source
The invention relates to a reference voltage source including a bipolar transistor having a base, a collector and an emitter electrode. The reference voltage...
US-6,737,354 Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates
An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that...
US-6,737,351 Versatile system for diffusion limiting void formation
Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device...
US-6,737,347 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
A semiconductor device and a method for making it involve the semiconductor device (10, 110, 210, 310) having a substrate (11, 311) with spaced source and drain...
US-6,737,333 Semiconductor device isolation structure and method of forming
A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer...
US-6,737,326 Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect
A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and...
US-6,737,325 Method and system for forming a transistor having source and drain extensions
According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a...
US-6,737,225 Method of undercutting micro-mechanical device with super-critical carbon dioxide
A method for removing sacrificial layers during the process of fabricating micro-mechanical devices with a solution of super-critical carbon dioxide. A mixture...
US-6,736,521 On axis translational motion stops for movable structure having torsional hinge
A device 21 comprises a movable structure 44 having a first movable portion 70 hinged to frame portion 60 by a first pair of hinges 81, 82 spaced apart along a...
US-6,735,737 Error correction structures and methods
A parallel Chien search by partitioning of the nonzero elements of a root field and using a parallel Galois multiplier.
US-6,735,724 Detection error estimation and method
A method of monitoring the performance of a Viterbi detector by using the deviations from the noiseless case of the path difference of the two branches entering...
US-6,735,668 Process of using a DRAM with address control data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,735,667 Synchronous data system with control data buffer
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,735,652 Detecting the occurrence of desired values on a bus
A circuit determining whether a present value transmitted on a bus equals any of several desired values. The circuit may contain a monitor random access memory...
US-6,735,260 Adaptive data slicer
An adaptive data slicer which functions to adapt to changes in the properties of a signal input thereto by producing a near optimal slicing threshold in...
US-6,735,146 System and method for pulling electrically isolated memory cells in a memory array to a non-floating state
In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more...
US-6,735,143 System for reducing power consumption in memory devices
The present invention provides a system for reducing power consumption in a memory device containing a memory array having a number of memory cells. The present...
US-6,735,106 Accelerated fatigue testing
A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be...
US-6,735,034 Relative timing sequence for reader amplifiers
A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a...
US-6,735,030 Method to write servo on multi-channels with voltage mode data and single channel with current mode data
A write drive circuit (40) for a hard disk drive selectively providing a current mode operation for high speed data write of a single channel, and selectively...
US-6,735,027 Head fly height by using the applied peak area ratio to determine signal PW50
The present invention includes a circuit and method for determining fly height based upon the PW50. A signal is used to provide a measure of PW50 by detecting...
US-6,734,743 Oscillation based cycle time measurement
An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a...
US-6,734,741 Frequency synthesizer with digitally-controlled oscillator
A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC...
US-6,734,738 Low power timer circuit having stable output frequency
A timer circuit having an oscillator circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 has highly stable...
US-6,734,736 Low power variable gain amplifier
A variable gain amplifier includes an input stage that receives an input signal and converts the input signal into a corresponding intermediate signal. An output...
US-6,734,721 Method and apparatus for affecting speed of transition of a closed loop circuit
A method for affecting speed of transition of a closed loop circuit from an initial state to a steady state during a transition period; the closed loop circuit...
US-6,734,711 Slow input transition stabilizer circuit
An input transition stabilizer circuit, adapted to stabilize an input transition of a signal appearing at the input of an input circuit, the input transition...
US-6,734,705 Technique for improving propagation delay of low voltage to high voltage level shifters
The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors...
US-6,734,702 Impedance calibration circuit
An impedance calibration circuit for a serial ATA (SATA) transmitter has a resistor in series with each leg of the differential output of the transmitter. An...
US-6,734,567 Flip-chip device strengthened by substrate metal ring
Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a...
US-6,734,532 Back side coating of semiconductor wafers
A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output...
US-6,734,521 Integrated circuit cells
According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a...
US-6,734,491 EEPROM with reduced manufacturing complexity
A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210)...
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