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Patent # Description
US-6,735,146 System and method for pulling electrically isolated memory cells in a memory array to a non-floating state
In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more...
US-6,735,143 System for reducing power consumption in memory devices
The present invention provides a system for reducing power consumption in a memory device containing a memory array having a number of memory cells. The present...
US-6,735,106 Accelerated fatigue testing
A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be...
US-6,735,034 Relative timing sequence for reader amplifiers
A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a...
US-6,735,030 Method to write servo on multi-channels with voltage mode data and single channel with current mode data
A write drive circuit (40) for a hard disk drive selectively providing a current mode operation for high speed data write of a single channel, and selectively...
US-6,735,027 Head fly height by using the applied peak area ratio to determine signal PW50
The present invention includes a circuit and method for determining fly height based upon the PW50. A signal is used to provide a measure of PW50 by detecting...
US-6,734,743 Oscillation based cycle time measurement
An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a...
US-6,734,741 Frequency synthesizer with digitally-controlled oscillator
A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC...
US-6,734,738 Low power timer circuit having stable output frequency
A timer circuit having an oscillator circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 has highly stable...
US-6,734,736 Low power variable gain amplifier
A variable gain amplifier includes an input stage that receives an input signal and converts the input signal into a corresponding intermediate signal. An output...
US-6,734,721 Method and apparatus for affecting speed of transition of a closed loop circuit
A method for affecting speed of transition of a closed loop circuit from an initial state to a steady state during a transition period; the closed loop circuit...
US-6,734,711 Slow input transition stabilizer circuit
An input transition stabilizer circuit, adapted to stabilize an input transition of a signal appearing at the input of an input circuit, the input transition...
US-6,734,705 Technique for improving propagation delay of low voltage to high voltage level shifters
The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors...
US-6,734,702 Impedance calibration circuit
An impedance calibration circuit for a serial ATA (SATA) transmitter has a resistor in series with each leg of the differential output of the transmitter. An...
US-6,734,567 Flip-chip device strengthened by substrate metal ring
Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a...
US-6,734,532 Back side coating of semiconductor wafers
A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output...
US-6,734,521 Integrated circuit cells
According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a...
US-6,734,491 EEPROM with reduced manufacturing complexity
A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210)...
US-6,734,477 Fabricating an embedded ferroelectric memory cell
Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a...
US-6,734,076 Method for thin film resistor integration in dual damascene structure
A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed...
US-6,734,073 Method for manufacturing a bipolar junction transistor
According to one embodiment of the invention, a method for manufacturing a bipolar junction transistor includes implanting a first base dopant in a semiconductor...
US-6,734,068 Method to form silicates as high dielectric constant materials
An embodiment of the instant invention is a method of forming a semiconductor device situated over a semiconductor substrate, the method comprising the steps of:...
US-6,733,683 Method of fabricating a cooperating array of rotatable microstructure devices
A method of manufacturing an array of microstructures, such as a micromirror array assembly (10, 20) for use in optical modules (5, 17) in a wireless network...
US-6,732,339 Cell-based noise characterization and evaluation
In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on...
US-6,732,315 Home networking over phone lines
A home networking transmitter (100), receiver (200), station (300), network manager (404), network (400) and method adapted to network devices (344/336/338/346)...
US-6,732,284 Processor having real-time power conservation
A processor, comprising a monitor for measuring the relative amount of idle time within the processor, results of the measuring being used by the processor,...
US-6,732,283 Processor having real-time power conservation
A processor, comprising a monitor for, depending on the respective embodiment, measuring the relative amount of idle time, activity time, or idle time and...
US-6,732,252 Memory interface device and memory address generation device
A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of...
US-6,732,226 Memory device for transferring streams of data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,732,225 Process for controlling reading data from a DRAM array
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,732,224 System with control data buffer for transferring streams of data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,731,917 Method and apparatus for minimizing image power in the output of a receiver circuit
A receiver system (10) includes a first stage of modulation (46, 51) which modulates a radio-frequency input signal (17), and a second stage of modulation (56,...
US-6,731,564 Method and system for power conservation in memory devices
According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a...
US-6,731,533 Loadless 4T SRAM cell with PMOS drivers
The instant invention comprises a memory cell with PMOS drive transistors (170, 180) and NMOS pass transistors (150, 160). A NMOS transistor is connected between...
US-6,731,420 Optical switching apparatus
An optical matrix switch station (1) is shown mounting a plurality of optical switch units (15, 17), each of which includes a mirror (29), moveable in two axes,...
US-6,731,406 Segmented multilevel screening for printing files in a page description language
This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time...
US-6,731,163 Miller de-compensation for differential input, differential output amplifier
A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential...
US-6,731,132 Programmable line terminator
A programmable line terminator device that can optimally terminate a transmission line or bus even if the line impedance is variable or not well defined. The...
US-6,731,127 Parallel integrated circuit test apparatus and test method
A test apparatus (300) comprising a single handler (304) is coupled to a first tester (336) and second tester (308). A first test procedure is performed on a set...
US-6,731,106 Measuring on-resistance of an output buffer with test terminals
The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary...
US-6,730,977 Lower temperature method for forming high quality silicon-nitrogen dielectrics
A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick...
US-6,730,962 Method of manufacturing and structure of semiconductor device with field oxide structure
A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of...
US-6,730,950 Local interconnect using the electrode of a ferroelectric
Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The...
US-6,730,616 Versatile plasma processing system for producing oxidation resistant barriers
A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and...
US-6,730,613 Method for reducing by-product deposition in wafer processing equipment
A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a...
US-6,730,597 Pre-ECD wet surface modification to improve wettability and reduced void defect
A pre-ECD wet surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with a water-based...
US-6,730,582 Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD)...
A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G.sub.2) in a fixed relationship to the ...
US-6,730,569 Field effect transistor with improved isolation structures
An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and...
US-6,730,566 Method for non-thermally nitrided gate formation for high voltage devices
A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the...
US-6,730,556 Complementary transistors with controlled drain extension overlap
An integrated circuit device (60) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type...
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