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Patent # Description
US-6,715,357 Hermetic pressure transducer
A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal...
US-6,715,058 Apparatus and method for a sorting mode in a direct memory access controller of a digital signal processor
In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the...
US-6,715,000 Method and device for providing high data rate for a serial peripheral interface
An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and...
US-6,714,774 Antenna reception diversity in wireless communications
Antenna reception diversity is provided for wireless communications such that a received signal (r) can be produced by combining antenna signals (v.sub.i) with...
US-6,714,766 Circuit assembly for producing a one-way connection between transmitter and/or receiver units and an antenna
In a circuit assembly for producing a one-way connection between a first transmitter or receiver (12) operating on a first frequency and an antenna (16), on the...
US-6,714,469 On-chip compression of charge distribution data
A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One...
US-6,714,338 MEM's mirror internal sensor linearization based on driver linearity
A technique that reduces or eliminates the non-linearities associated with the internal feedback sensor used in a micro-electro-mechanical mirror assembly. Using...
US-6,714,336 Packaged micromirror assembly with in-package mirror position feedback
A packaged micromirror assembly (21, 21') is disclosed. The assembly (21, 21') includes a mirror element (41) having a mirror surface (29) that can rotate in two...
US-6,714,002 Integrated semiconductor circuit and multi-chip module with a plurality of integrated semiconductor circuits
An integrated semiconductor circuit (10) with function inputs (14a) and function outputs (16a), as well as with function units (12), which supply the function...
US-6,713,881 Semiconductor device and method of manufacturing same
Object: To provide sufficient connection strength between the bonding pads and conductor wires in a wire bonding method. Means for Solution: The bonding pads 20 upon...
US-6,713,852 Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin
A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure...
US-6,713,851 Lead over chip semiconductor device including a heat sink for heat dissipation
The invention relates to an LOC type semiconductor device having improved heat radiation. The semiconductor device related to the present invention has a...
US-6,713,848 Output stage layout for minimum cross coupling between channels
An audio amplifier output stage layout technique achieves minimum cross coupling between audio amplifier channels. Regarding TDAA output stages, the typical TDAA...
US-6,713,676 System and method for converting a DC input voltage to a DC output voltage
A system for converting a DC input voltage to a DC output voltage includes at least one integrated circuit die electrically coupled to a leadframe. An inductor...
US-6,713,402 Methods for polymer removal following etch-stop layer etch
Cleaning methods are disclosed for removing sidewall polymers from interconnect vias or trenches, wherein a wafer is exposed to a plasma comprising hydrogen and...
US-6,713,361 Method of manufacturing a bipolar junction transistor including undercutting regions adjacent to the emitter...
According to one embodiment of the invention, a method for manufacturing bipolar junction transistors includes disposing a first oxide layer between a...
US-6,713,360 System for reducing segregation and diffusion of halo implants into highly doped regions
The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor...
US-6,713,342 FeRAM sidewall diffusion barrier etch
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the...
US-6,713,334 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask
An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the...
US-6,713,311 Method for screening semiconductor devices for contact coplanarity
A method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts. The method includes the steps of measuring the...
US-6,712,475 Housing and internal layout for compact SLM-based projector
A display system based on a spatial light modulator (SLM). Various embodiments of the invention all involve some sort of articulating element, such that the...
US-6,711,904 Active thermal management of semiconductor devices
The present invention facilitates semiconductor cooling by combining a semiconductor die and a thermoelectric cooler into a single, integrated package or system....
US-6,711,707 Process of controlling plural test access ports
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-6,711,683 Compresses video decompression system with encryption of compressed data stored in video buffer
A secure computing system prevents unauthorized use of compressed video data stored in a first-in-first-out memory buffer in a set top box. A single integrated...
US-6,711,602 Data processor with flexible multiply unit
An embodiment of the invention includes a pair of parallel 16.times.16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow...
US-6,711,599 Limit-cycle-absent allpass filter lattice structure
A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232,...
US-6,710,959 Input pole compensation for a disk drive read head
An adjustable impedance boosting circuit for a magneto-resistive head in a gain stage beyond the input gain stage. The boosting circuit compensates for a...
US-6,710,788 Graphical user interface
A graphical user interface uses a representation of a polyhedron, such as a cube (44), having images on each face (46) for representing multiple desktops used in...
US-6,710,695 Aircraft circuit breaker with manual opening resistant feature
A pushbutton resettable circuit breaker is shown having features to prevent manual opening by simply pulling outwardly on the pushbutton. In one embodiment, the...
US-6,710,655 Bipolar emitter couple pair transconductor for high speed operational amplifiers
An emitter coupled pair transconductor circuit includes: an emitter couple pair 20 and 21; and a tail current source coupled to the emitter couple pair wherein...
US-6,710,654 Bipolar class AB folded cascode operational amplifier for high-speed applications
The present invention (800) comprises an operational amplifier with a first stage comparator circuit (801) for biasing a second stage folded cascode amplifier...
US-6,710,632 Drive circuit
A drive circuit including circuitry that can be easily adjusted, the output drive current can be kept balanced, and high-precision drive current can be supplied...
US-6,710,507 Digital control loop to solve instability of electrostatic drives beyond 1/3 gap limit
A circuit (40) and method are provided to create a drive voltage that is linearly proportional to a position of a movable member (12) of an electrostatic...
US-6,710,443 INTEGRATED CIRCUIT PROVIDING THERMALLY CONDUCTIVE STRUCTURES SUBSTANTIALLY HORIZONTALLY COUPLED TO ONE ANOTHER...
In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat...
US-6,710,427 Distributed power device with dual function minority carrier reduction
A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each...
US-6,710,391 Integrated DRAM process/structure using contact pillars
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The...
US-6,710,364 Semiconductor wafer edge marking
The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20') is disclosed. The information may be marked by...
US-6,709,974 Method of preventing seam defects in isolated lines
A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of...
US-6,709,948 Process for manufacturing a two-axis mirror
A process for manufacturing a wafer from a layer of material such as silicon and having a multiplicity of MEMS devices such as mirrors with gimbals formed...
US-6,709,938 Source/drain extension fabrication process with direct implantation
An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without...
US-6,709,932 Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process
One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating...
US-6,709,900 Method of fabricating integrated system on a chip protection circuit
A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to...
US-6,709,875 Contamination control for embedded ferroelectric device fabrication processes
A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible...
US-6,709,113 Reduction of moire effect in pixelated rear-projection displays
An apparatus and method for reducing the moire effect in rear-projection displays by rotating the dark-stripe structure (711, 712) in the screen (71) 45.+-.15...
US-6,708,303 Method and apparatus for controlling a seperate scan output of a scan circuit
A scan circuit (10) has a scan data input (17), a normal data input (18), a clock input (22), a scan enable input (19), a normal data output (23), and a scan...
US-6,708,290 Configurable debug system with wire list walking
The invention relates to a software system and method for automatically determining capabilities of a hardware system to permit a software development system to...
US-6,708,125 Procedure for the determination of the consumption of electrical energy
Procedure for the determination of the consumption of electrical energy by a consumer in a procedure for the determination of the consumption of electrical...
US-6,708,082 System identification to improve control of a micro-electro-mechanical mirror
A method of adjusting a MEMS mirror control system is provided to calibrate a MEMS mirror control system to a particular MEMS mirror in a fashion that optimizes...
US-6,707,936 Method and apparatus for predicting device yield from a semiconductor wafer
Device design information (18) for a semiconductor device is used to generate theoretical probability of failure information (21), which represents the...
US-6,707,902 Method of resynchronizing data transfer between two modems connected by a dedicated line
A method of resynchronizing data transfer between a first modem assigned to a central office and connected by a dedicated line a second modem assigned to a...
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