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Patent # Description
US-6,734,477 Fabricating an embedded ferroelectric memory cell
Integrated circuit structures comprising an embedded ferroelectric memory cell and methods of forming the same are described. These structures include a...
US-6,734,076 Method for thin film resistor integration in dual damascene structure
A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed...
US-6,734,073 Method for manufacturing a bipolar junction transistor
According to one embodiment of the invention, a method for manufacturing a bipolar junction transistor includes implanting a first base dopant in a semiconductor...
US-6,734,068 Method to form silicates as high dielectric constant materials
An embodiment of the instant invention is a method of forming a semiconductor device situated over a semiconductor substrate, the method comprising the steps of:...
US-6,733,683 Method of fabricating a cooperating array of rotatable microstructure devices
A method of manufacturing an array of microstructures, such as a micromirror array assembly (10, 20) for use in optical modules (5, 17) in a wireless network...
US-6,732,339 Cell-based noise characterization and evaluation
In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on...
US-6,732,315 Home networking over phone lines
A home networking transmitter (100), receiver (200), station (300), network manager (404), network (400) and method adapted to network devices (344/336/338/346)...
US-6,732,284 Processor having real-time power conservation
A processor, comprising a monitor for measuring the relative amount of idle time within the processor, results of the measuring being used by the processor,...
US-6,732,283 Processor having real-time power conservation
A processor, comprising a monitor for, depending on the respective embodiment, measuring the relative amount of idle time, activity time, or idle time and...
US-6,732,252 Memory interface device and memory address generation device
A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of...
US-6,732,226 Memory device for transferring streams of data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,732,225 Process for controlling reading data from a DRAM array
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,732,224 System with control data buffer for transferring streams of data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,731,917 Method and apparatus for minimizing image power in the output of a receiver circuit
A receiver system (10) includes a first stage of modulation (46, 51) which modulates a radio-frequency input signal (17), and a second stage of modulation (56,...
US-6,731,564 Method and system for power conservation in memory devices
According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a...
US-6,731,533 Loadless 4T SRAM cell with PMOS drivers
The instant invention comprises a memory cell with PMOS drive transistors (170, 180) and NMOS pass transistors (150, 160). A NMOS transistor is connected between...
US-6,731,420 Optical switching apparatus
An optical matrix switch station (1) is shown mounting a plurality of optical switch units (15, 17), each of which includes a mirror (29), moveable in two axes,...
US-6,731,406 Segmented multilevel screening for printing files in a page description language
This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time...
US-6,731,163 Miller de-compensation for differential input, differential output amplifier
A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential...
US-6,731,132 Programmable line terminator
A programmable line terminator device that can optimally terminate a transmission line or bus even if the line impedance is variable or not well defined. The...
US-6,731,127 Parallel integrated circuit test apparatus and test method
A test apparatus (300) comprising a single handler (304) is coupled to a first tester (336) and second tester (308). A first test procedure is performed on a set...
US-6,731,106 Measuring on-resistance of an output buffer with test terminals
The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary...
US-6,730,977 Lower temperature method for forming high quality silicon-nitrogen dielectrics
A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick...
US-6,730,962 Method of manufacturing and structure of semiconductor device with field oxide structure
A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of...
US-6,730,950 Local interconnect using the electrode of a ferroelectric
Ferroelectric device structures are provided comprising a ferroelectric capacitor, first and second circuit elements, and first and second contacts. The...
US-6,730,616 Versatile plasma processing system for producing oxidation resistant barriers
A versatile system for forming diffusion barriers in semiconductor processing that simplifies device processing, utilizing existing production compounds and...
US-6,730,613 Method for reducing by-product deposition in wafer processing equipment
A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a...
US-6,730,597 Pre-ECD wet surface modification to improve wettability and reduced void defect
A pre-ECD wet surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with a water-based...
US-6,730,582 Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (ESD)...
A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G.sub.2) in a fixed relationship to the ...
US-6,730,569 Field effect transistor with improved isolation structures
An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and...
US-6,730,566 Method for non-thermally nitrided gate formation for high voltage devices
A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the...
US-6,730,556 Complementary transistors with controlled drain extension overlap
An integrated circuit device (60) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type...
US-6,730,555 Transistors having selectively doped channel regions
An integrated semiconductor system is provided that is formed on a substrate 10. A dual implant mask 26 is used to change the characteristics of semiconductor...
US-6,730,554 Multi-layer silicide block process
An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125)...
US-6,730,541 Wafer-scale assembly of chip-size packages
A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a...
US-6,730,354 Forming ferroelectric Pb(Zr,Ti)O3 films
Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These...
US-6,729,947 Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
US-6,729,886 Method of fabricating a drain isolated LDMOS device
A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a...
US-6,728,950 Method and apparatus for translating between source and target code
An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source...
US-6,728,928 Modified viterbi detector for jitter noise dominant channels
A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to .lambda..sub.k.sup.(i)...
US-6,728,915 IC with shared scan cells selectively connected in scan path
This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in...
US-6,728,838 Cache operation based on range of addresses
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory...
US-6,728,829 Synchronous DRAM system with control data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,728,828 Synchronous data transfer system
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,728,741 Hardware assist for data block diagonal mirror image transformation
A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises...
US-6,728,320 Capacitive data and clock transmission between isolated ICs
A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first...
US-6,728,302 STTD encoding for PCCPCH
A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a...
US-6,728,301 System and method for automatic frequency control in spread spectrum communications
A method is providing for calculating local oscillator phase errors in a code division multiple access (CDMA) receiver using an arctangent calculation of the...
US-6,728,128 Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device...
US-6,728,056 Current stealing circuit to control the impedance of a TGMR head amplifier biasing circuit regardless of...
An impedance controlling circuit (152) is connected across an MR head (42) and has two current paths, each including a control transistor (154,156), a current...
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