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Patent # Description
US-9,329,234 IC die test, scan, and capture, shift, and update circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,329,233 TAP with AUX capture input, gated capture and shiftDR outputs
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,...
US-9,329,232 Scan response reuse method and apparatus
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and...
US-9,329,231 Serial input/output, source/destination bus data multiplexer, flip flop, and controller circuitry
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-9,329,230 Enable and select inputs operate combinational logic parallel scan paths
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the...
US-9,325,373 Broadcast transmission for multi-tone mask mode operation
A method of Multi-Tone Mask (MTM) mode communications in a PLC network including a first router associated with a plurality of nodes. A super-frame spanning a...
US-9,325,334 IC, process, device generating frequency reference from RF gas absorption
A frequency reference device that includes a frequency reference generation unit to generate a frequency reference signal based on an absorption line of a gas.
US-9,325,327 Circuits and method of equalizing impedances of PMOS and NMOS devices
A circuit for equalizing the impedances of a PMOS device with an NMOS device includes a first reference voltage coupled to the source of the first PMOS device....
US-9,325,241 Dead-time compensation in a power supply system
One embodiment includes a power supply system. The system includes a pulse-width modulation (PWM) system configured to generate a PWM signal. The system also...
US-9,325,233 DC to DC converter and PWM controller with adaptive compensation circuit
DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency...
US-9,324,856 MOSFET having dual-gate cells with an integrated channel diode
A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region....
US-9,324,717 High mobility transistors
An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have...
US-9,324,640 Triple stack semiconductor package
A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality...
US-9,323,071 Laser speckle reduction for uniform illumination
Laser speckle reduction using a passive diffuser. A diffuser for reducing laser speckle is disclosed comprising a diffuser having a colloid configured for...
US-9,322,879 Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask...
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-9,322,877 TMS/TDI and SIPO controller circuitry with tap and trace interfaces
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI...
US-9,322,875 Core circuitry, test access mechanism, scan frame input register, decompressor
Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The...
US-9,322,863 Embedded SAR based active gain capacitance measurement system and method
A system for measuring a capacitor (C.sub.SENj) precharges a CDAC (23) in a SAR converter (17) to a reference voltage (V.sub.AZ) and also precharges a first...
US-9,321,631 Method for embedding controlled-cavity MEMS package in integration board
A method for fabricating a micro-electro-mechanical system (MEMS) provides a semiconductor chip having a cavity with a radiation sensor MEMS. The opening of the...
US-9,319,928 Link adaptation for LTE uplink
A detailed design of an LTE Link Adaptation function for LTE uplink is disclosed. A new approach for adapting SINR backoff in OLLA is used when serving...
US-9,319,238 Overlapping priority contention windows power line communications networks
Embodiments of a power line communication (PLC) transmitter device for overlapping priority contention windows are presented. A processor is configured to...
US-9,319,121 4TX codebook enhancement in LTE
Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based...
US-9,319,095 DSSS inverted spreading for smart utility networks
A method of operating a transmitter (FIGS. 3A and 5A) is disclosed. The method includes receiving a sequence of data bits (DATA), wherein each data bit has a...
US-9,319,059 Calibrated SAR ADC having a reduced size
The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital...
US-9,319,045 Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a...
A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip includes a...
US-9,318,897 Reducing corruption of communication in a wireless power transmission system
An embodiment of the invention provides a method for reducing data corruption in a wireless power transmission system. Power is transmitted from a primary coil...
US-9,318,598 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
US-9,318,337 Three dimensional three semiconductor high-voltage capacitors
An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the...
US-9,318,222 Hierarchical, distributed built-in self-repair solution
A built-in self-test (BIST) circuit to test one or more memory blocks on an integrated circuit. The one or more memory blocks further includes a first memory...
US-9,317,049 Emulated current ramp for DC-DC converter
A voltage converter (FIG. 4) for a power supply circuit is disclosed. The voltage converter comprises a control circuit (400) coupled to receive an enable (EN)...
US-9,316,692 Tap clock and enable control of scan register, flip-flop, comparator
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device...
US-9,313,799 Method of controlling communication of data packets based on different communication standards, a dual platform...
A dual platform communication controller, a method of controlling communication of data packets based on different communication standards and a wireless...
US-9,313,513 Detection of resynchronization markers when decoding an MPEG-4 bitstream
A method for detecting a resynchronization marker in an encoded MPEG-4 video bitstream is provided that includes computing a first candidate resynchronization...
US-9,313,127 Rotate-mask-merge and deposit-field instructions for packet processing
In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second...
US-9,313,124 Conditional instructions for packet processing
A network switch includes a plurality of ports, a parser coupled to the plurality of ports, and a processor coupled to the ports and configured to process a...
US-9,313,062 Transmission of acknowledge/not acknowledge (ACK/NACK) bits and their embedding in the reference signal
Transmitting a acknowledge/not acknowledge (ACK/NACK) response in a wireless cellular network by mapping the data value into a cyclic shifted version of a...
US-9,312,591 Dielectric waveguide with corner shielding
A dielectric wave guide (DWG) has a longitudinal dielectric core member. The core member has a first dielectric constant value. A cladding surrounds the...
US-9,312,253 Heterogeneous integration of memory and split-architecture processor
A method for fabricating a semiconductor device provides a first chip having first terminals, a second chip having second terminals, and a third chip having...
US-9,312,170 Metal on elongated contacts
An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including...
US-9,312,164 Localized region of isolated silicon over dielectric mesa
An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the...
US-9,311,989 Power gate for latch-up prevention
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the...
US-9,311,274 Approach for significant improvement of FFT performance in microcontrollers
A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by...
US-9,310,919 Adaptive thresholding for touch screen input
An adaptive threshold approach is applied to detect true touch signals and filter out increased noise signals. More specifically, statistics regarding the...
US-9,310,868 Charging a provider/consumer with a dead battery via USB power delivery
A method and apparatus are provided. The VBUS conductor is checked to determine whether the voltage on the VBUS conductor is greater than a vSafe0V voltage...
US-9,310,861 Robust cable-type detection for USB power delivery
A system and method for detecting a USB cable-type. A USB PD device configured at a near end of a USB cable is configured to (i) receive and process a signal...
US-9,310,823 Voltage reference
A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar...
US-9,310,434 Scan topology discovery in target systems
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
US-9,308,620 Permeated grooving in CMP polishing pads
A polishing pad for polishing a semiconductor wafer or other materials, having grooves in the polishing pad to enhance the usable lifetime of the polishing pad.
US-9,307,262 Methods and systems for facilitating multimedia data encoding utilizing configured buffer information
Several methods and systems for facilitating multimedia data encoding are disclosed. In an embodiment, a plurality of picture buffers associated with multimedia...
US-9,306,743 One-way key fob and vehicle pairing verification, retention, and revocation
Embodiments of the invention provide methods for key fob to control unit verification, retention, and revocation. After an initial pairing between a key fob and...
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