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Patent # Description
US-6,730,554 Multi-layer silicide block process
An integrated circuit resistor (170) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (125)...
US-6,730,541 Wafer-scale assembly of chip-size packages
A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a...
US-6,730,354 Forming ferroelectric Pb(Zr,Ti)O3 films
Improved methods of forming PZT thin films that are compatible with industry-standard chemical vapor deposition production techniques are described. These...
US-6,729,947 Semiconductor wafer handler
A semiconductor wafer handler comprises a ring (70) attached to a hub (80) by a plurality of spokes (90). Vacuum is applied to the surface of the semiconductor...
US-6,729,886 Method of fabricating a drain isolated LDMOS device
A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a...
US-6,728,950 Method and apparatus for translating between source and target code
An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source...
US-6,728,928 Modified viterbi detector for jitter noise dominant channels
A Viterbi detector includes circuitry for receiving an NRZ encoded received signal in an EEPR4 channel to decode the signal according to .lambda..sub.k.sup.(i)...
US-6,728,915 IC with shared scan cells selectively connected in scan path
This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in...
US-6,728,838 Cache operation based on range of addresses
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory...
US-6,728,829 Synchronous DRAM system with control data
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,728,828 Synchronous data transfer system
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,728,741 Hardware assist for data block diagonal mirror image transformation
A data processing apparatus and method for quickly and efficiently producing a diagonally (170) mirrored image of a block of data (168). The apparatus comprises...
US-6,728,320 Capacitive data and clock transmission between isolated ICs
A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first...
US-6,728,302 STTD encoding for PCCPCH
A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a...
US-6,728,301 System and method for automatic frequency control in spread spectrum communications
A method is providing for calculating local oscillator phase errors in a code division multiple access (CDMA) receiver using an arctangent calculation of the...
US-6,728,128 Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device...
US-6,728,056 Current stealing circuit to control the impedance of a TGMR head amplifier biasing circuit regardless of...
An impedance controlling circuit (152) is connected across an MR head (42) and has two current paths, each including a control transistor (154,156), a current...
US-6,727,757 Biasing circuit for transconductors
A transconductor circuit, including a differential transconductor amplifier circuit. The transconductor circuit includes an input pair of transistors adapted to...
US-6,727,755 High speed linear variable gain amplifier architecture
A two stage amplifier circuit (10), the first stage (12) comprising a modified quad configuration and the second stage (14) comprising a translinear current...
US-6,727,752 Modulation scheme for switching amplifiers to reduce filtering requirements and crossover distortion
A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a...
US-6,727,722 Process of testing a semiconductor wafer of IC dies
Integrated circuit die on a wafer are tested individually, without probing any of the die, using circuitry (TC1-8, BC1-8, LR1-8, RR1-8, PA1-PA4) provided on the...
US-6,727,578 Semiconductor device having power supply voltage routed through substrate
A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped...
US-6,727,185 Dry process for post oxide etch residue removal
A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues (116).
US-6,727,133 Integrated circuit resistors in a high performance CMOS process
An integrated circuit resistor (150) is formed on an isolation dielectric structure (20) formed in a semiconductor (10). A patterned silicon nitride layer (74)...
US-6,727,131 System and method for addressing junction capacitances in semiconductor devices
A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a...
US-6,725,409 DSP instruction for turbo decoding
The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor....
US-6,725,391 Clock modes for a debug port with on the fly clock switching
An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a...
US-6,725,202 Transaction accounting of toll transactions in transponder systems
This invention allows a toll authority to monitor transaction numbers which are sent from a transponder (14) to an interrogator (12). By incrementing the...
US-6,725,025 Interference cancellation among wireless units using Gibbs sampling
An improved interference cancellation technique is disclosed. Digital baseband circuitry (40) includes user and symbol detection circuitry (50) for performing a...
US-6,724,828 Mobile switching between STTD and non-diversity mode
A communication circuit is designed with a detector circuit (720) coupled to receive a first signal. The detector circuit is arranged to produce a multipath...
US-6,724,646 Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device...
US-6,724,556 Single pole voltage bias loop for increased stability
A differential circuit to read differential data from a disk by a voltage bias includes a read circuit having a read circuit pole to read the differential data...
US-6,724,551 Preamp fast head switch technique for servo mode
A differential circuit to read differential data from a disk by a current bias on a plurality of read heads includes a read circuit to read the differential data...
US-6,724,431 Program network specific information for TV or radio
A communication system is desccribed which comprises a transmitter which transmits a standard broadcast format with an associated text string and a receiver for...
US-6,724,327 Lower latency coding/decoding
An electronic device may receive a packet comprising a plurality of codewords comprising pre-processing logic, a first decoder, and a second decoder. The...
US-6,724,264 Controller for a device with change in characteristics
A device characteristic changing apparatus is provided for changing a characteristic of a device. The device characteristic changing apparatus comprises a time...
US-6,724,260 Low power current feedback amplifier
A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a...
US-6,724,258 Highly-linear, wide-input-range, wide control-range, low-voltage differential voltage controlled transconductor
A voltage controlled transconductor (VCT) for receiving a differential input signal comprising a first voltage signal and a second voltage signal, and for...
US-6,724,236 Buffered bootstrapped input switch with cancelled charge sharing for use in high performance sample and hold...
A buffered bootstrapped input switch employs cancelled charge sharing for use in high performance sample and hold switched capacitor circuits especially useful...
US-6,724,070 Fine pitch lead frame
A lead frame including a first set of leads in a first plane and a second set of leads in a second plane offset vertically from the second plane. The leads in...
US-6,724,066 High breakdown voltage transistor and method
An integrated circuit that includes a high breakdown voltage bipolar transistor. The bipolar transistor includes an emitter 36, a base 32, and a collector...
US-6,724,050 ESD improvement by a vertical bipolar transistor with low breakdown voltage and high beta
A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity...
US-6,724,047 Body contact silicon-on-insulator transistor and method
A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly...
US-6,723,658 Gate structure and method
A MOSFET structure with silicate gate dielectrics and silicon or metal gates with HF-based wet silicate gate dielectric etch.
US-6,723,636 Methods for forming multiple damascene layers
According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via...
US-6,723,629 Method and apparatus for attaching solder members to a substrate
The invention discloses a method for attaching solder members (114) to a substrate (112). The method includes forming a decal (110) with a plurality of solder...
US-6,723,616 Process of increasing screen dielectric thickness
A method of forming a semiconductor device using shallow trench isolation, includes forming a trench within a semiconductor substrate and forming a screen...
US-6,723,172 Method and system for processing semiconductor wafers
A method for processing semiconductor wafers includes processing a semiconductor wafer in a processing chamber having upper and lower chambers, decoupling the...
US-6,722,210 System and method for measuring air flow at multiple points of an air channel
A device measures air flow at multiple points in an air channel. The device includes a metering plate that has multiple passages through the metering plate. The...
US-6,721,774 Low power multiplier
A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23...
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