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Patent # Description
US-6,713,334 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask
An implant at HVGX pattern (step 102c) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the...
US-6,713,311 Method for screening semiconductor devices for contact coplanarity
A method for determining contact coplanarity of packaged semiconductor devices having a plurality of contacts. The method includes the steps of measuring the...
US-6,712,475 Housing and internal layout for compact SLM-based projector
A display system based on a spatial light modulator (SLM). Various embodiments of the invention all involve some sort of articulating element, such that the...
US-6,711,904 Active thermal management of semiconductor devices
The present invention facilitates semiconductor cooling by combining a semiconductor die and a thermoelectric cooler into a single, integrated package or system....
US-6,711,707 Process of controlling plural test access ports
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-6,711,683 Compresses video decompression system with encryption of compressed data stored in video buffer
A secure computing system prevents unauthorized use of compressed video data stored in a first-in-first-out memory buffer in a set top box. A single integrated...
US-6,711,602 Data processor with flexible multiply unit
An embodiment of the invention includes a pair of parallel 16.times.16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow...
US-6,711,599 Limit-cycle-absent allpass filter lattice structure
A lattice-based second-order allpass filter (200) providing a digital filter, absent of limit cycles, includes interconnected quantizers(214, 224), delays (232,...
US-6,710,959 Input pole compensation for a disk drive read head
An adjustable impedance boosting circuit for a magneto-resistive head in a gain stage beyond the input gain stage. The boosting circuit compensates for a...
US-6,710,788 Graphical user interface
A graphical user interface uses a representation of a polyhedron, such as a cube (44), having images on each face (46) for representing multiple desktops used in...
US-6,710,695 Aircraft circuit breaker with manual opening resistant feature
A pushbutton resettable circuit breaker is shown having features to prevent manual opening by simply pulling outwardly on the pushbutton. In one embodiment, the...
US-6,710,655 Bipolar emitter couple pair transconductor for high speed operational amplifiers
An emitter coupled pair transconductor circuit includes: an emitter couple pair 20 and 21; and a tail current source coupled to the emitter couple pair wherein...
US-6,710,654 Bipolar class AB folded cascode operational amplifier for high-speed applications
The present invention (800) comprises an operational amplifier with a first stage comparator circuit (801) for biasing a second stage folded cascode amplifier...
US-6,710,632 Drive circuit
A drive circuit including circuitry that can be easily adjusted, the output drive current can be kept balanced, and high-precision drive current can be supplied...
US-6,710,507 Digital control loop to solve instability of electrostatic drives beyond 1/3 gap limit
A circuit (40) and method are provided to create a drive voltage that is linearly proportional to a position of a movable member (12) of an electrostatic...
US-6,710,443 INTEGRATED CIRCUIT PROVIDING THERMALLY CONDUCTIVE STRUCTURES SUBSTANTIALLY HORIZONTALLY COUPLED TO ONE ANOTHER...
In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat...
US-6,710,427 Distributed power device with dual function minority carrier reduction
A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each...
US-6,710,391 Integrated DRAM process/structure using contact pillars
A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The...
US-6,710,364 Semiconductor wafer edge marking
The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20') is disclosed. The information may be marked by...
US-6,709,974 Method of preventing seam defects in isolated lines
A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of...
US-6,709,948 Process for manufacturing a two-axis mirror
A process for manufacturing a wafer from a layer of material such as silicon and having a multiplicity of MEMS devices such as mirrors with gimbals formed...
US-6,709,938 Source/drain extension fabrication process with direct implantation
An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without...
US-6,709,932 Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process
One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating...
US-6,709,900 Method of fabricating integrated system on a chip protection circuit
A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to...
US-6,709,875 Contamination control for embedded ferroelectric device fabrication processes
A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible...
US-6,709,113 Reduction of moire effect in pixelated rear-projection displays
An apparatus and method for reducing the moire effect in rear-projection displays by rotating the dark-stripe structure (711, 712) in the screen (71) 45.+-.15...
US-6,708,303 Method and apparatus for controlling a seperate scan output of a scan circuit
A scan circuit (10) has a scan data input (17), a normal data input (18), a clock input (22), a scan enable input (19), a normal data output (23), and a scan...
US-6,708,290 Configurable debug system with wire list walking
The invention relates to a software system and method for automatically determining capabilities of a hardware system to permit a software development system to...
US-6,708,125 Procedure for the determination of the consumption of electrical energy
Procedure for the determination of the consumption of electrical energy by a consumer in a procedure for the determination of the consumption of electrical...
US-6,708,082 System identification to improve control of a micro-electro-mechanical mirror
A method of adjusting a MEMS mirror control system is provided to calibrate a MEMS mirror control system to a particular MEMS mirror in a fashion that optimizes...
US-6,707,936 Method and apparatus for predicting device yield from a semiconductor wafer
Device design information (18) for a semiconductor device is used to generate theoretical probability of failure information (21), which represents the...
US-6,707,902 Method of resynchronizing data transfer between two modems connected by a dedicated line
A method of resynchronizing data transfer between a first modem assigned to a central office and connected by a dedicated line a second modem assigned to a...
US-6,707,702 Volatile memory with non-volatile ferroelectric capacitors
Memory apparatus and methods are provided for storing data in a semiconductor device, comprising volatile and non-volatile portions, where the non-volatile...
US-6,707,690 Power converter employing switched split transformer primary
A pulse-width modulated apparatus to convert an input voltage to an output voltage at advantaged duty-cycles utilizes more than two switches in a converter...
US-6,707,629 Digital temperature monitor
A digital temperature monitor (DTM (24) includes a proportional-to-absolute temperature (PTAT) sensor (44) and reference circuit (48) coupled to the inputs of a...
US-6,707,404 Integral nonlinearity error correction circuitry and method for DAC
An M+N bit DAC includes an N-bit interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor (17A) and a second voltage (Vlow)...
US-6,707,282 Switched control of inductor ringing for a boost switched power supply
A power supply circuit for generating regulated voltages includes a storage circuit to store the voltages, a control circuit to control the level of stored...
US-6,707,135 Semiconductor leadframe for staggered board attach
The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities,...
US-6,707,124 HID land grid array packaged device having electrical and optical interconnects
A high density interconnect device which creates a thin, electrically and thermally high performance package for semiconductor devices having a mechanically...
US-6,706,635 Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis
The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion...
US-6,706,623 Method and system for avoiding plasma etch damage
An electronic device and method of construction are disclosed that provide for a dielectric layer (12) having a low dielectric constant. A conductive sheath...
US-6,706,606 Buried zener diode structure and method of manufacture
A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down...
US-6,706,605 Transistor formed from stacked disposable sidewall spacer
A method of forming an integrated circuit transistor (80), comprising providing a semiconductor region (90) and forming a gate structure (92, 94) in a fixed...
US-6,706,561 Method for fabricating preplated nickel/palladium and tin leadframes
A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a...
US-6,704,903 Simplified branch metric and method
A branch metric computation using limited bits by clipping the dynamic range and/or approximating the square of the difference between a sample value and the...
US-6,704,895 Integrated circuit with emulation register in JTAG JAP
An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and...
US-6,704,847 Host access to shared memory with a high priority mode
A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access...
US-6,704,582 Personalized incoming call signal for communication devices
Apparatus and methods are presented to allow the creation of a personalized audio signal for a communication device., An option to record audio input and create...
US-6,704,218 FeRAM with a single access/multiple-comparison operation
A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison...
US-6,704,132 Micromirror truss structure and fabrication method
A micromirror (110) includes a frame portion (112), a gimbal portion (114) and a mirror portion (116) formed from a single piece of material. A plurality of...
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