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Patent # Description
US-6,750,910 Optical black and offset correction in CCD signal processing
An apparatus for providing optical black and offset calibration for an array signal comprising a sequence of voltage levels corresponding to a sequence of...
US-6,750,909 Image buffer between burst memory and data processor with multiple access modes set by the data processor
An image processing system comprising a burst memory; a data processor; and a data buffer coupled between the burst memory and the data processor. The data...
US-6,750,699 Power supply independent all bipolar start up circuit for high speed bias generators
A start up circuit includes: a diode Q0; a first transistor Q1 coupled in series with the diode Q0; a first resistor R4 coupled in series with the first...
US-6,750,694 Signal clipping circuit
A clipping circuit (20) for clipping an input signal to a level corresponding to a regulated power supply voltage (AVDD). The clipping circuit (20) includes a...
US-6,750,676 Driving circuit
A driving circuit reduces fall delay time, and the output timing of a driving current can be controlled highly accurately while reducing ringing during a...
US-6,750,663 Method and system for conducting continuity testing on analog devices having sensitive input nodes
The present invention provides for a method (30) and system (10) for isolating the input nodes (3, 4) and/or the output nodes (5, 8) of an analog device (12) and...
US-6,750,641 Method and circuit for temperature nonlinearity compensation and trimming of a voltage reference
An exemplary method and circuit for temperature nonlinearity compensation and trimming of a voltage reference are configured to provide for two-point independent...
US-6,750,553 Semiconductor device which minimizes package-shift effects in integrated circuits by using a thick metallic...
A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition...
US-6,750,543 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced...
US-6,750,134 Variable cross-section plated mushroom with stud for bumping
An improved bump fabrication process is described that produces a larger diameter/taller solder ball than with a standard mushroom by forming an elongated...
US-6,750,126 Methods for sputter deposition of high-k dielectric films
Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or...
US-6,750,081 Header for electronic components board in surface mount and through-hole assembly
A low-cost header for connecting an electronic components board to a circuit board is disclosed, consisting of side walls made of an unwarpable plastic material...
US-6,749,443 Socket for mounting an electronic device
A socket (10) has a base member (20), a cover member (30) which is mounted for alternating motion toward and away from base member (20), a plurality of contacts...
US-6,748,521 Microprocessor with instruction for saturating and packing data
A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands...
US-6,748,483 Process of operating a DRAM system
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit...
US-6,748,363 TI window compression/expansion method
According to the present invention, there is developed a proprietary technology for compressing the window tables of audio coders to 1/8 their original size (or...
US-6,748,006 Method and apparatus for controlling system timing with use of a master timer
Unique methods and apparatus for maintaining timing in spread spectrum communications are described. One method involves the steps of repeatedly incrementing an...
US-6,747,858 Digital sample rate converter architecture
A digital sample rate converter converts a digital input signal (Din) having a first sample rate (Fs_in) to a corresponding digital output signal Dout having a...
US-6,747,827 Error correction codes applied variably by disk zone, track, sector, or content
A method for performing error correction code operations on data to be read from the disk (12) of a hard disk drive (10) includes applying a first error...
US-6,747,630 Method to up-sample frequency rich images without significant loss of image sharpness
A bi-cosine filter having a scaling technique to process images for up-scaling that does not lead to loss of the high frequency content of the generated image...
US-6,747,626 Dual mode thin film transistor liquid crystal display source driver circuit
The present invention relates to a source driver circuit (200) for driving a thin film transistor liquid crystal display (TFT-LCD) panel. The source driver...
US-6,747,589 Error correction architecture to increase speed and relax current drive requirements of SAR ADC
An SAR ADC is operated by sampling an input voltage and redistributing a corresponding charge among the coupling capacitor and a plurality of binarily weighted...
US-6,747,507 Bias generator with improved stability for self biased phase locked loop
A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP4; a second transistor MP3 coupled in parallel with...
US-6,747,504 Controlled rise time output driver
A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides...
US-6,747,498 CAN receiver wake-up circuit
A wake-up circuit for a ECU on a CAN bus utilizes two complementary switching transistors which will turn ON when there is a differential voltage between CANH...
US-6,747,481 Adaptive algorithm for electrical fuse programming
This invention describes a means for preventing eFuses from growing back under successive programming pulses after being successfully fused by an earlier set of...
US-6,747,441 Non-synchronous switching regulator with improved output regulation at light or low loads
A switching power supply or switching regulator is provided with a control circuit that controls a switching signal to a first switch. The switching signal is...
US-6,747,353 Barrier layer for copper metallization in integrated circuit fabrication
A barrier layer (20, 62) for an integrated circuit structure is disclosed. The barrier layer (20, 62) is a refractory metal silicon compound, such as a refractor...
US-6,747,343 Aluminum leadframes with two nickel layers
A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of...
US-6,747,308 Single poly EEPROM with reduced area
An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate...
US-6,746,886 MEMS device with controlled gas space chemistry
A process for protecting a MEMS device used in a UV illuminated application from damage due to a photochemical activation between the UV flux and package gas...
US-6,745,319 Microprocessor with instructions for shuffling and dealing data
A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the...
US-6,745,293 Level 2 smartcache architecture supporting simultaneous multiprocessor accesses
A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having...
US-6,744,757 Private branch exchange systems for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,744,533 Efficient buffer rendering
A method and system for efficient buffer rendering. An object mask, typically a character font mask, is aligned with a memory tiling arrangement (1102). A tile...
US-6,744,280 Voltage output differential (VOD) correction circuit for differential drivers
System and methods are provided for monitoring circuit performance and correcting for variations in current reference signals to maintain a desired Voltage...
US-6,744,243 System and method for dynamically regulating a step down power supply
A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the...
US-6,744,034 Micro-electromechanical apparatus and method with position sensor compensation
Micro-electromechanical apparatus and method with position sensor compensation to compensate for sensor drift. A preferred embodiment comprises modifying the...
US-6,743,719 Method for forming a conductive copper structure
The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of...
US-6,743,705 Transistor with improved source/drain extension dopant concentration
A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in...
US-6,743,684 Method to produce localized halo for MOS transistor
Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a...
US-6,743,656 MEMS wafer level package
An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer...
US-6,742,395 Hermetic pressure transducer
A port fitting (102) is formed with a closed, pedestal end forming a diaphragm (102a) on which a strain gauge sensor is mounted. A support member (106) is...
US-6,742,110 Preventing the execution of a set of instructions in parallel based on an indication that the instructions were...
A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first...
US-6,742,104 Master/slave processing system with shared translation lookaside buffer
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide...
US-6,742,103 Processing system with shared translation lookaside buffer
A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses .mu.TLBs (36) and a shared TLB subsystem (48) to provide...
US-6,742,058 Memory controller having a multiplexer selecting either second set of input signals or converted signals from...
A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The...
US-6,741,750 Motion artifact correction in exposure systems
A system and method for correcting spatial banding artifacts in print images. The system includes: a light source, a spatial light modulator, a transport system...
US-6,741,611 Packet memory management (PACMAN) scheme
The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of...
US-6,741,503 SLM display data address mapping for four bank frame buffer
A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into...
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