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Generating netlist test vectors by stripping references to a pseudo input
A method for enabling test vectors to be generated for a customer designed integrated circuit having an embedded vendor circuit is disclosed. The embedded vendor...
Cache with block prefetch and DMA
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory...
Wireless communications apparatus
Apparatus for a wireless communication network, comprises: a directional beam antenna, an antenna controller for directing said directional beam antenna in an...
Digital signal processing acoustic speaker system
A technique for realizing high-speed and high-precision acoustic reproduction using acoustic speakers. The audio signal processing system has a sub-band analysis...
Digital programmable, spread spectrum clock generator
A digital spread spectrum clock generator. The generator includes a digital waveform generator adapted to generate a sequence of digital words representing a...
Method and system for steering a collimated light beam with a pivotable
An optical system 200 includes a light source 202, such as a laser diode. A rotatable mirror 208 is positioned to receive a light beam 220 from the light source...
Fast frame readout architecture for array sensors with integrated
correlated double sampling system
A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse...
Tone display method
A tone display method which prevents degradation in image quality of moving images when the subfield method is utilized without an increase in cost. When tone...
System and method for dynamic element matching
Dynamic element matching systems and methods are provided in which a current dynamic element matching code is generated according to a previous dynamic element...
Apparatus for generating at least one digital output signal representative
of an analog signal
An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section...
Method for implementing high frequency programmable poles and zeros in disk
A pole and zero circuit for changing the position of a pole, or a zero, of an amplifier including a capacitor to change the position of the pole or zero for the...
Switch mode regulator controller using hybrid technique
A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP...
Reduction of external component count in variable voltage integrated DC/DC
A variable DC/DC converter system is provided that includes a feedback voltage device and a compensation device. The compensation device and compensation...
Contact structure for reliable metallic interconnection
A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is...
Polymer-embedded solder bumps for reliable plastic package attachment
A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each...
Method of manufacturing a semiconductor integrated circuit device having a
memory cell array and a peripheral...
In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate...
Bilayer deposition to avoid unwanted interfacial reactions during high K
gate dielectric processing
Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a...
Low power testing of very large circuits
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
Low overhead input and output boundary scan cells
Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of...
Configuration bus reconfigurable/reprogrammable interface for expanded
direct memory access processor
The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip....
Talking book method and system
A talking book and a method of authoring a talking book is presented where the talking book includes a synthesizer, an audio system, a memory, a display, and...
Offset correction of the output of a charge coupled device
An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for...
Path to trapezoid decomposition of polygons for printing files in a page
This invention cures many inefficiencies with known scan conversion methods. This invention employs an edge array rather than a set linked list from an array of...
System and method for implementing soft power up
A system and method are disclosed to help protect a node of associated circuitry from overshooting or undershooting, such as can be associated with power up or...
Methods and semiconductor devices with wiring layer fill structures to
improve planarization uniformity
Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect...
Copper transition layer for improving copper interconnection reliability
The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said...
Post-etch cleaning treatment
The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant...
Versatile flow cell front-end for optically-based integrated sensors
A versatile flow cell front-end (104) for storing and delivering reagents, test samples, and other transportable materials within an optically-based integrated...
Sacrificial anode for corrosion protection of semiconductor metallization
Resistance to corrosion of aluminum metallization on semiconductor devices during wafer sawing process is provided by a sacrificial anode containing magnesium in...
Hot liner insertion/removal fixture
A fixture (30) adapted to permit the heated exchange of a liner (14) from an operating vertical furnace (10). The fixture is adapted to secure to the base of the...
Memory management in embedded system with design time object instantiation
A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is...
System and method of implementing variabe length delay instructions, which
prevents overlapping lifetime...
A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a...
Shared program memory for use in multicore DSP devices
A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because...
Dual sequencer based disk formatter
The present invention provides for a dual sequencer for use in a peripheral storage device system, as well as a new protocol for data retrieval/storage in...
Capture and conversion of mixed-signal test stimuli
A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion...
Method for establishing and maintaining optical, open-air communications
A method for controlling an optical, path-to-sight link, the optical link including a source of light having a beam of light, a controllable beam steering device...
Flexible Viterbi decoder for wireless applications
A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric...
Modular interconnection of network switches
Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20)...
Security system to enable authenticated access of an individual to a
A security system to enable authenticated access of an individual to a protected area, including a remote control unit (22) with a transponder (28), carried by...
Delay circuit with current steering output symmetry and supply voltage
A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal...
Bandgap voltage reference insensitive to voltage offset
A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has...
LDO voltage regulator having efficient current frequency compensation
A low drop out linear voltage regulator (200) overcomes the dynamic quiescent current limitation by creating an internal zero that moves in the same direction...
Minimization and linearization of ESD parasitic capacitance in integrated
An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive...
System and method for electroplating fine geometries
An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is...
Process for fabricating ball grid array package for enhanced stress
The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like...
Modeling technique for selectively depopulating electrical contacts from a
foot print of a grid array (BGA or...
A modeling technique for selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a...
Railing for a boat conveyor system
A conveyor system (30) comprises: a boat (20), a feed belt (36), a feed pulley (38), and improved railings (34). The boat (20) is adapted to carry a component or...
Optimized metal fuse process
A metal fuse process that uses a thinner (e.g., 6000 .ANG.) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for...
Multi-channel DMA with request scheduling
A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source...
Method and apparatus for transmitting control information across a
serialized bus interface
A bus interface device includes a parallel input configured to be coupled to a bus (20), such as a primary PCI bus. The device also includes a parallel data...