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Apparatus and method of connecting and interfacing active device components
A method and apparatus of connecting an active computing device (15) to an active peripheral option (20) comprising the steps of making a physical connection...
Dual purpose serial/parallel data transfer device for peripheral storage
A peripheral storage device system and a data transfer device for use in a peripheral storage device system are disclosed, which provide for selective...
Serial peripheral interface with high performance buffering scheme
The serial peripheral interface and high performance buffering scheme according to the present invention addresses many of the shortcomings of the prior art. In...
Condition responsive sense system and method
An application specific integrated circuit or ASIC (MSC) is connected to a plurality of bridge type sense elements (1-6) for analog multiplexing (10a, 10b, 10c)...
Implementing RF power measurements in a broadband communications device
The invention provides systems, methods, and devices that compensate for temperature, frequency, and sampling effects in a broadband communication device's power...
Method and system for generating image compression quantization matrices
A system (100) for generating image compression matrices is disclosed. The present invention includes an image (102) having pixel block arrays (104). The present...
High-speed long code generation with arbitrary delay
A circuit is designed with a first register circuit (364) arranged to store a state matrix. A memory circuit (710) is arranged to store a plurality of ...
Timing phase acquisition method and device for telecommunications systems
A timing phase acquisition method and device for burst modems includes an receiver designed to initialize an equalizer filter by matching clock of the equalizer...
Static random access memory cell and method
A method for forming a scaled static random access memory (SRAM) cell (10) based on an initial SRAM cell for implementation in a technology scaled from an...
Conductive member grid array interface for mirror array drive apparatus
The present invention discloses drive apparatus for rotating a mirror used for switching light signals. The drive apparatus has reduced internal wiring and uses...
Write head fault detection circuit and method
A circuit (30, 40) and method for detecting faults of a write head (18) of a hard-disk drive system (70). A first resistor R.sub.1 and a second resistor R.sub.2...
Reducing short circuit power in CMOS inverter circuits
A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback...
DC/DC switching regulator having reduced switching loss
A DC/DC switching regulator has a semiconductor switch coupled to an inductor, a first capacitor and a rectifier. A circuit to improve the switching efficiency...
Sub-critical-dimension integrated circuit features
A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a...
Undercut process with isotropic plasma etching at package level
A method (30) of fabricating a micromechanical device (10) by performing spacer layer undercutting (46) and passivation at the package level. A back-end assembly...
Shallow trench isolation planarization using self aligned isotropic etch
A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed...
High precision integrated circuit capacitors
A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer...
Methods of preventing reduction of IrOx during PZT formation by
metalorganic chemical vapor deposition or other...
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of...
Method of separating semiconductor dies from a wafer
Methods are disclosed for manufacturing semiconductor device dies and for separating dies from a semiconductor wafer, wherein one or more channels are etched in...
Methods for controlling the crystallographic texture of thin films with
anisotropic ferroelectric polarization...
A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment...
Two-exposure phase shift photolithography with improved inter-feature
A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same...
Method and apparatus for stretching and processing saw film tape after
breaking a partially sawn wafer
A method and apparatus for separating a wafer into wafer portions comprising a larger wafer flex-frame (50) supported on a support base (40) and a smaller...
Method for interfacing a cardbay card to the host system by indicating a
16-bit or cardbus PC card insertion to...
The present invention provides a method, system and apparatus of interfacing a CardBay device (520) using existing Card and Socket Services (CSS) software (530)....
Task based priority arbitration
A digital system and method of operation is provided in which several processors (1400, 1402, 1404) are connected to a shared resource (1432). Each processor has...
In-situ randomization and recording of wafer processing order at process
Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing...
System and method for advanced interfaces for virtual environments
A system and method for providing a controllable virtual environment includes a computer (11) with processor and a display coupled to the processor to display...
Soft start circuit for regulated power supply
A power supply feedback circuit includes a regulating element at an input side of an optical isolator. The control lead for the regulating element is connected...
Integrated circuit with bonding layer over active circuitry
An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E)....
Methods of and apparatus for manufacturing ball grid array semiconductor
A method of manufacturing a ball grid array semiconductor package includes the step of providing a substrate (103) having a first surface (103b) and a second...
Constant light disable for spatial light modulator
A method and system of detecting whether the intensity of light incident a spatial light modulator varies periodically. One embodiment provides a method of...
Methods for transistor gate formation using gate sidewall implantation
Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are...
Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine
The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion...
Cathodic sputtering chamber for applying material to the surface of a
semiconductor wafer located therein
A chamber (10) for applying material to the surface of a semiconductor wafer (18) located in the chamber by means of cathodic sputtering a target (26), located...
Dual access instruction and compound memory access instruction with
compatible address fields
A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured...
Software controlled cache configuration based on average miss rate
A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a...
Effective channel priority processing for transfer controller with hub and
A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a...
Method for constructing a metal oxide semiconductor field effect transistor
A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region...
Space efficient interconnect test multi-structure
The present invention relates to a test structure and a method for forming a test structure over a semiconductor substrate. The test structure comprises a...
Si-rich surface layer capped diffusion barriers
A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is...
Methods and devices for optimized digital and analog CMOS transistor
performance in deep submicron technology
High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket...
System and method of regulating the distribution of power throughout a
system through the use of...
An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit...
Cache/smartcache with interruptible block prefetch
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment memory circuit....
Digital filter with efficient quantization circuitry
An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable...
Image information encoding system
An image information encoding system that includes detecting an image portion for which higher image quality is desired based on the motion vector value and the...
Wireless telephone with excitation reconstruction of lost packet
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
Reduced standby power memory array and method
A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a...
Quad state memory design methods, circuits, and systems
As the number of signaling wires increase in integrated circuits, power consumption, related to charging and discharging of wiring capacitance also increases and...
Second order active RC filter with imaginary zero
A stop band second order active RC filter architecture that does not use a non-inverting input to receive an input signal, and that employs both positive and...
Shallow trench isolation step height detection method
A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the...
Overcurrent sensing using high side switch device in switching power
A DC-DC switching regulator, adapted to receive a pulsed signal. The regulator includes an inductor, and also includes a capacitor having one port connected to...