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Patent # Description
US-6,686,210 Methods for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization...
A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment...
US-6,686,102 Two-exposure phase shift photolithography with improved inter-feature separation
A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same...
US-6,685,073 Method and apparatus for stretching and processing saw film tape after breaking a partially sawn wafer
A method and apparatus for separating a wafer into wafer portions comprising a larger wafer flex-frame (50) supported on a support base (40) and a smaller...
US-6,684,283 Method for interfacing a cardbay card to the host system by indicating a 16-bit or cardbus PC card insertion to...
The present invention provides a method, system and apparatus of interfacing a CardBay device (520) using existing Card and Socket Services (CSS) software (530)....
US-6,684,280 Task based priority arbitration
A digital system and method of operation is provided in which several processors (1400, 1402, 1404) are connected to a shared resource (1432). Each processor has...
US-6,684,125 In-situ randomization and recording of wafer processing order at process tools
Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing...
US-6,683,625 System and method for advanced interfaces for virtual environments
A system and method for providing a controllable virtual environment includes a computer (11) with processor and a display coupled to the processor to display...
US-6,683,443 Soft start circuit for regulated power supply
A power supply feedback circuit includes a regulating element at an input side of an optical isolator. The control lead for the regulating element is connected...
US-6,683,380 Integrated circuit with bonding layer over active circuitry
An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E)....
US-6,683,371 Methods of and apparatus for manufacturing ball grid array semiconductor device packages
A method of manufacturing a ball grid array semiconductor package includes the step of providing a substrate (103) having a first surface (103b) and a second...
US-6,683,290 Constant light disable for spatial light modulator
A method and system of detecting whether the intensity of light incident a spatial light modulator varies periodically. One embodiment provides a method of...
US-6,682,994 Methods for transistor gate formation using gate sidewall implantation
Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are...
US-6,682,980 Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion...
US-6,682,635 Cathodic sputtering chamber for applying material to the surface of a semiconductor wafer located therein
A chamber (10) for applying material to the surface of a semiconductor wafer (18) located in the chamber by means of cathodic sputtering a target (26), located...
US-6,681,319 Dual access instruction and compound memory access instruction with compatible address fields
A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured...
US-6,681,297 Software controlled cache configuration based on average miss rate
A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a...
US-6,681,270 Effective channel priority processing for transfer controller with hub and ports
A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a...
US-6,680,504 Method for constructing a metal oxide semiconductor field effect transistor
A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region...
US-6,680,484 Space efficient interconnect test multi-structure
The present invention relates to a test structure and a method for forming a test structure over a semiconductor substrate. The test structure comprises a...
US-6,680,249 Si-rich surface layer capped diffusion barriers
A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is...
US-6,680,226 Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology
High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket...
US-6,678,829 System and method of regulating the distribution of power throughout a system through the use of...
An integrated solution to power management and distribution on a power bus, such as needed for an IEEE 1394 compliant expansion board. The integrated circuit...
US-6,678,797 Cache/smartcache with interruptible block prefetch
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment memory circuit....
US-6,678,709 Digital filter with efficient quantization circuitry
An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable...
US-6,678,324 Image information encoding system
An image information encoding system that includes detecting an image portion for which higher image quality is desired based on the motion vector value and the...
US-6,678,267 Wireless telephone with excitation reconstruction of lost packet
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
US-6,678,202 Reduced standby power memory array and method
A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a...
US-6,678,188 Quad state memory design methods, circuits, and systems
As the number of signaling wires increase in integrated circuits, power consumption, related to charging and discharging of wiring capacitance also increases and...
US-6,677,815 Second order active RC filter with imaginary zero
A stop band second order active RC filter architecture that does not use a non-inverting input to receive an input signal, and that employs both positive and...
US-6,677,766 Shallow trench isolation step height detection method
A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the...
US-6,677,738 Overcurrent sensing using high side switch device in switching power converters
A DC-DC switching regulator, adapted to receive a pulsed signal. The regulator includes an inductor, and also includes a capacitor having one port connected to...
US-6,677,735 Low drop-out voltage regulator having split power device
The present invention provides a low drop-out voltage regulator (200) that reduces gate capacitance and simplifies the compensation needed to maintain stability,...
US-6,677,240 Method for patterning dense and isolated features on semiconductor devices
According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a...
US-6,677,232 Method for fabricating metal conductors and multi-level interconnects in a semiconductor device
A method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device. The method also...
US-6,677,208 Transistor with bottomwall/sidewall junction capacitance reduction region and method
A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a...
US-6,677,207 Vanishingly small integrated circuit diode
An embodiment of the instant invention is a method of implementing a vanishingly small integrated circuit diode comprising the steps of: forming an area of a...
US-6,677,201 Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor...
A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer...
US-6,677,190 Self-aligned body contact in a semiconductor device
A method of forming an electrical contact is provided. The method includes forming a gate dielectric layer adjacent a body region of a transistor structure and...
US-6,677,188 Methods for forming a fuse in a semiconductor device
According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The...
US-6,675,342 Direct comparison adaptive halting decoder and method of use
A direct comparison adaptive halting turbo decoder computes the sum of the a priori and the extrinsic information sequences at each iteration step. The sum...
US-6,675,334 Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for...
A circuit comprising a data input and output, a memory interface, a programmable counter, a signal line, and a test circuit further comprising an instruction...
US-6,675,333 Integrated circuit with serial I/O controller
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is...
US-6,675,331 Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch
A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10),...
US-6,674,621 IC PMOS Schottky reverse bias protection structure
The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source...
US-6,674,620 Hermetic single phase motor protector
A hermetic motor protector (10) has a non-current carrying snap-acting thermostatic disc (26) freely disposed on a disc seat (22a) having a tab (22c) projecting...
US-6,674,595 Controlled impedance amplifiers
A hard disk drive (HDD) circuit (10) having feedback provided to an input of an differential amplifier setting the amplifier input impedance close to a flexible...
US-6,674,591 Method and apparatus for identifying a track of a rotating disk using EPR4 data equalization and detection...
According to a broad aspect of the invention, a method and apparatus are presented for identifying a track (42) of a rotating disk (12) of a mass data storage...
US-6,674,435 Fast, symmetric, integer bezier curve to polygon conversion
A printer forms an approximate of a Bezier curve as a sequence of line segments. Two parametric equations, X(t) and Y(t), are employed. Two methods can be used...
US-6,674,381 Methods and apparatus for tone reduction in sigma delta modulators
Sigma delta modulators and digital to analog converters therefor are disclosed, in which intentional mismatch is provided in circuit elements of the digital to...
US-6,674,359 Method of identifying several transponders
Transponders present in an interrogation zone can be identified by an interrogator by it sending an RF interrogation signal into the interrogation zone, the RF...
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