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Patent # Description
US-6,677,735 Low drop-out voltage regulator having split power device
The present invention provides a low drop-out voltage regulator (200) that reduces gate capacitance and simplifies the compensation needed to maintain stability,...
US-6,677,240 Method for patterning dense and isolated features on semiconductor devices
According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a...
US-6,677,232 Method for fabricating metal conductors and multi-level interconnects in a semiconductor device
A method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device. The method also...
US-6,677,208 Transistor with bottomwall/sidewall junction capacitance reduction region and method
A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a...
US-6,677,207 Vanishingly small integrated circuit diode
An embodiment of the instant invention is a method of implementing a vanishingly small integrated circuit diode comprising the steps of: forming an area of a...
US-6,677,201 Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor...
A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer...
US-6,677,190 Self-aligned body contact in a semiconductor device
A method of forming an electrical contact is provided. The method includes forming a gate dielectric layer adjacent a body region of a transistor structure and...
US-6,677,188 Methods for forming a fuse in a semiconductor device
According to one embodiment of the invention, a method is provided. The method includes lining, with a conductive liner, a surface of a dielectric layer. The...
US-6,675,342 Direct comparison adaptive halting decoder and method of use
A direct comparison adaptive halting turbo decoder computes the sum of the a priori and the extrinsic information sequences at each iteration step. The sum...
US-6,675,334 Apparatus and method for multi-cycle memory access mapped to JTAG finite state machine with external flag for...
A circuit comprising a data input and output, a memory interface, a programmable counter, a signal line, and a test circuit further comprising an instruction...
US-6,675,333 Integrated circuit with serial I/O controller
A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is...
US-6,675,331 Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch
A transparent latch (18) and a logic conditioning circuit (10) are disclosed. The transparent latch (18) receives signals from conditioning circuit (10),...
US-6,674,621 IC PMOS Schottky reverse bias protection structure
The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source...
US-6,674,620 Hermetic single phase motor protector
A hermetic motor protector (10) has a non-current carrying snap-acting thermostatic disc (26) freely disposed on a disc seat (22a) having a tab (22c) projecting...
US-6,674,595 Controlled impedance amplifiers
A hard disk drive (HDD) circuit (10) having feedback provided to an input of an differential amplifier setting the amplifier input impedance close to a flexible...
US-6,674,591 Method and apparatus for identifying a track of a rotating disk using EPR4 data equalization and detection...
According to a broad aspect of the invention, a method and apparatus are presented for identifying a track (42) of a rotating disk (12) of a mass data storage...
US-6,674,435 Fast, symmetric, integer bezier curve to polygon conversion
A printer forms an approximate of a Bezier curve as a sequence of line segments. Two parametric equations, X(t) and Y(t), are employed. Two methods can be used...
US-6,674,381 Methods and apparatus for tone reduction in sigma delta modulators
Sigma delta modulators and digital to analog converters therefor are disclosed, in which intentional mismatch is provided in circuit elements of the digital to...
US-6,674,359 Method of identifying several transponders
Transponders present in an interrogation zone can be identified by an interrogator by it sending an RF interrogation signal into the interrogation zone, the RF...
US-6,674,316 Methods and apparatus for trimming electrical devices
Trimming methods and apparatus are disclosed for selectively removing resistance between first and second nodes in an electrical device, including trim circuits...
US-6,673,400 Hydrogen gettering system
A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed...
US-6,672,170 Hermetic pressure transducer
A port fitting is formed with a closed, pedestal end forming a diaphragm on which a strain gauge sensor is mounted. A support member is received on the pedestal...
US-6,671,797 Microprocessor with expand instruction for forming a mask from one bit
A data processing system is provided with a digital signal processor which has an instruction for expanding one bit to form a mask field. In one form of the...
US-6,671,765 Architecture enabling code overlay using a dedicated endpoint
A USB function device (14) for coupling to a USB host (12). The USB function device (14), comprises circuitry (32) for providing a capability to the USB host,...
US-6,671,665 Emulation system with search and identification of optional emulation peripherals
In-circuit-emulation of an integrated circuit permits location and identification of optional emulation resources. Each emulation resource is assigned a memory...
US-6,671,663 Time domain noise analysis
A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time...
US-6,670,828 Programmable termination for CML I/O
A programmable termination circuit (12) selectively providing a termination voltage to a driver or receiver of a high-speed serial link, such as CML I/O's. The...
US-6,670,685 Method of manufacturing and structure of semiconductor device with floating ring structure
A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide...
US-6,668,366 System and method for processing a transistor channel layout
A system for processing a transistor channel layout includes a processor coupled to an input device, an output device, a memory, and a data retrieval device. The...
US-6,668,345 Synchronous semiconductor allowing replacement with redundant memory cell while maintaining access time
The higher order bit of the output from an address latch circuit is applied to a predecoder that operates a predecode signal to select a column select line and...
US-6,668,008 Ultra-wide band communication system and method
A system and method for generating an ultra-wide band communication signal having data occurring a specific frequencies precisely excised at baseband. The data...
US-6,667,993 Communication channel
A digital system (100) has two or more nodes (120, 130) and a communication channel (110, 111) for transferring a single stream of ordered data from one node to...
US-6,667,896 Grouped plate line drive architecture and method
An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of...
US-6,667,865 Efficient design of substrate triggered ESD protection circuits
A semiconductor device is designed with a common supply voltage terminal (330). A plurality of standard cells (360-364), each having a plurality of leads...
US-6,667,650 Current leakage compensation circuit and method
A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The...
US-6,667,597 Method of extending the operating speed range of a rotor flux based MRAS speed observer in a three phase AC...
A method of AC induction motor speed control employing a rotor flux based MRAS (Model Reference Adaptive System) speed observer. Rotor flux-based MRAS speed...
US-6,667,560 Board on chip ball grid array
A package for an integrated circuit includes a circuit board 122 for mounting the integrated circuit 114 having a first surface and a second surface, a...
US-6,667,433 Frequency and phase interpolation in sinusoidal model-based music and speech synthesis
A quadratic phase interpolation method for synthesis of musical tones incorporates both phase and frequency measurements at the boundaries of a data frame using...
US-6,667,231 Method of forming barrier films for copper metallization over low dielectric constant insulators in an...
An integrated circuit structure and method of making the same is disclosed, in which the adhesion of copper conductors (12, 22) to a low-dielectric constant...
US-6,667,226 Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure (108) is formed proximate a surface...
US-6,667,210 Flash memory cell process using a hardmask
A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch...
US-6,666,691 Socket for removably mounting electronic packages
A socket (1) has a base (2) on which rows of contact pins 4 are arranged, the contact pins being elastically deformable in the vertical direction, an adaptor (5)...
US-6,665,767 Programmer initiated cache block operations
This invention enables a program controlled cache state operation on a program designated address range. The program controlled cache state operation could be...
US-6,665,696 Delayed adaptive least-mean-square digital filter
A delayed adaptive least-mean-square (LMS) filter, which has one filter coefficient per tap and acquires a new data sample each frame, calculates a finite...
US-6,665,695 Delayed adaptive least-mean-square digital filter
A delayed adaptive least-mean-square (LMS) filter, which has one filter coefficient per tap and acquires a new data sample each frame, calculates a finite...
US-6,665,693 Digital signal processing circuits, systems, and methods implementing approximations for a reciprocal
A digital signal system (10, 100) for determining an approximate reciprocal of a value of x. The system includes an input (12) for receiving a signal, and...
US-6,665,277 Comma free codes for fast cell search using tertiary synchronization channel
A method of processing data comprises the receiving a frame of data having a predetermined number of time slots (502,504,506). Each time slot comprises a...
US-6,665,110 Diagonal to rectangular pixel mapping for spatial light modulator
A method of mapping diagonal rows and columns of two-dimensional grid elements to rectangular rows and columns of two-dimensional grid elements. The method is of...
US-6,664,912 Preamplifier with improved CMRR and temperature stability and associated amplification method
A preamplifier that is substantially resilient to temperature and input common-mode variations includes a feedback network coupled to regulate a common mode...
US-6,664,847 CTAT generator using parasitic PNP device in deep sub-micron CMOS process
A control circuit generates a current that remains substantially constant over temperature using a bandgap reference for providing a PTAT current. A first...
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