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Patent # Description
US-6,693,719 Path to trapezoid decomposition of polygons for printing files in a page description language
This invention cures many inefficiencies with known scan conversion methods. This invention employs an edge array rather than a set linked list from an array of...
US-6,693,478 System and method for implementing soft power up
A system and method are disclosed to help protect a node of associated circuitry from overshooting or undershooting, such as can be associated with power up or...
US-6,693,357 Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect...
US-6,693,356 Copper transition layer for improving copper interconnection reliability
The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said...
US-6,692,976 Post-etch cleaning treatment
The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant...
US-6,692,697 Versatile flow cell front-end for optically-based integrated sensors
A versatile flow cell front-end (104) for storing and delivering reagents, test samples, and other transportable materials within an optically-based integrated...
US-6,692,633 Sacrificial anode for corrosion protection of semiconductor metallization during sawing
Resistance to corrosion of aluminum metallization on semiconductor devices during wafer sawing process is provided by a sacrificial anode containing magnesium in...
US-6,692,249 Hot liner insertion/removal fixture
A fixture (30) adapted to permit the heated exchange of a liner (14) from an operating vertical furnace (10). The fixture is adapted to secure to the base of the...
US-6,691,298 Memory management in embedded system with design time object instantiation
A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is...
US-6,691,240 System and method of implementing variabe length delay instructions, which prevents overlapping lifetime...
A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a...
US-6,691,216 Shared program memory for use in multicore DSP devices
A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because...
US-6,691,186 Dual sequencer based disk formatter
The present invention provides for a dual sequencer for use in a peripheral storage device system, as well as a new protocol for data retrieval/storage in...
US-6,691,077 Capture and conversion of mixed-signal test stimuli
A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion...
US-6,690,888 Method for establishing and maintaining optical, open-air communications link
A method for controlling an optical, path-to-sight link, the optical link including a source of light having a beam of light, a controllable beam steering device...
US-6,690,750 Flexible Viterbi decoder for wireless applications
A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric...
US-6,690,668 Modular interconnection of network switches
Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20)...
US-6,690,259 Security system to enable authenticated access of an individual to a protected area
A security system to enable authenticated access of an individual to a protected area, including a remote control unit (22) with a transponder (28), carried by...
US-6,690,242 Delay circuit with current steering output symmetry and supply voltage insensitivity
A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal...
US-6,690,228 Bandgap voltage reference insensitive to voltage offset
A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has...
US-6,690,147 LDO voltage regulator having efficient current frequency compensation
A low drop out linear voltage regulator (200) overcomes the dynamic quiescent current limitation by creating an internal zero that moves in the same direction...
US-6,690,066 Minimization and linearization of ESD parasitic capacitance in integrated circuits
An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive...
US-6,689,686 System and method for electroplating fine geometries
An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is...
US-6,689,678 Process for fabricating ball grid array package for enhanced stress tolerance
The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like...
US-6,689,634 Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or...
A modeling technique for selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a...
US-6,688,453 Railing for a boat conveyor system
A conveyor system (30) comprises: a boat (20), a feed belt (36), a feed pulley (38), and improved railings (34). The boat (20) is adapted to carry a component or...
US-6,687,973 Optimized metal fuse process
A metal fuse process that uses a thinner (e.g., 6000 .ANG.) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for...
US-6,687,796 Multi-channel DMA with request scheduling
A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source...
US-6,687,779 Method and apparatus for transmitting control information across a serialized bus interface
A bus interface device includes a parallel input configured to be coupled to a bus (20), such as a primary PCI bus. The device also includes a parallel data...
US-6,687,777 Apparatus and method of connecting and interfacing active device components
A method and apparatus of connecting an active computing device (15) to an active peripheral option (20) comprising the steps of making a physical connection...
US-6,687,775 Dual purpose serial/parallel data transfer device for peripheral storage device
A peripheral storage device system and a data transfer device for use in a peripheral storage device system are disclosed, which provide for selective...
US-6,687,769 Serial peripheral interface with high performance buffering scheme
The serial peripheral interface and high performance buffering scheme according to the present invention addresses many of the shortcomings of the prior art. In...
US-6,687,642 Condition responsive sense system and method
An application specific integrated circuit or ASIC (MSC) is connected to a plurality of bridge type sense elements (1-6) for analog multiplexing (10a, 10b, 10c)...
US-6,687,489 Implementing RF power measurements in a broadband communications device
The invention provides systems, methods, and devices that compensate for temperature, frequency, and sampling effects in a broadband communication device's power...
US-6,687,412 Method and system for generating image compression quantization matrices
A system (100) for generating image compression matrices is disclosed. The present invention includes an image (102) having pixel block arrays (104). The present...
US-6,687,376 High-speed long code generation with arbitrary delay
A circuit is designed with a first register circuit (364) arranged to store a state matrix. A memory circuit (710) is arranged to store a plurality of ...
US-6,687,292 Timing phase acquisition method and device for telecommunications systems
A timing phase acquisition method and device for burst modems includes an receiver designed to initialize an equalizer filter by matching clock of the equalizer...
US-6,687,145 Static random access memory cell and method
A method for forming a scaled static random access memory (SRAM) cell (10) based on an initial SRAM cell for implementation in a technology scaled from an...
US-6,687,132 Conductive member grid array interface for mirror array drive apparatus
The present invention discloses drive apparatus for rotating a mirror used for switching light signals. The drive apparatus has reduced internal wiring and uses...
US-6,687,064 Write head fault detection circuit and method
A circuit (30, 40) and method for detecting faults of a write head (18) of a hard-disk drive system (70). A first resistor R.sub.1 and a second resistor R.sub.2...
US-6,686,773 Reducing short circuit power in CMOS inverter circuits
A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback...
US-6,686,729 DC/DC switching regulator having reduced switching loss
A DC/DC switching regulator has a semiconductor switch coupled to an inductor, a first capacitor and a rectifier. A circuit to improve the switching efficiency...
US-6,686,300 Sub-critical-dimension integrated circuit features
A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a...
US-6,686,291 Undercut process with isotropic plasma etching at package level
A method (30) of fabricating a micromechanical device (10) by performing spacer layer undercutting (46) and passivation at the package level. A back-end assembly...
US-6,686,283 Shallow trench isolation planarization using self aligned isotropic etch
A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed...
US-6,686,237 High precision integrated circuit capacitors
A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer...
US-6,686,236 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other...
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of...
US-6,686,225 Method of separating semiconductor dies from a wafer
Methods are disclosed for manufacturing semiconductor device dies and for separating dies from a semiconductor wafer, wherein one or more channels are etched in...
US-6,686,210 Methods for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization...
A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment...
US-6,686,102 Two-exposure phase shift photolithography with improved inter-feature separation
A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same...
US-6,685,073 Method and apparatus for stretching and processing saw film tape after breaking a partially sawn wafer
A method and apparatus for separating a wafer into wafer portions comprising a larger wafer flex-frame (50) supported on a support base (40) and a smaller...
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