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Patent # Description
US-6,700,445 Filter circuits based on trans-conductor circuits
A filter circuit uses a trans-conductor circuit coupled to a control circuit having similar characteristics as the trans-conductor circuit. The control circuit...
US-6,700,399 High density parasitic measurement structure
A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) overlying a substrate of...
US-6,700,360 Output stage compensation circuit
An output stage compensation circuit and method for a low drop-out regulator configured to facilitate stable operation while providing output voltage and current...
US-6,700,359 Method for simultaneous output ramp up of multiple regulators
An apparatus for generating a supply voltage includes a first regulator for generating a first supply voltage, a second regulator for generating a second supply...
US-6,700,350 Method and apparatus for controlling charge balance among cells while charging a battery array
A method for controlling voltage levels among cells while charging a battery array to a target voltage uses cell balancing modes employing respective charging...
US-6,700,160 Double-diffused MOS (DMOS) power transistor with a channel compensating implant
An improved DMOS power transistor (20) with a single p-body implant (12) and including an n-type channel compensating implant (NCCI) (24). The improved DMOS...
US-6,699,771 Process for optimizing junctions formed by solid phase epitaxy
A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method...
US-6,699,763 Disposable spacer technology for reduced cost CMOS processing
A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium...
US-6,699,745 Capacitor and memory structure and method
A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also...
US-6,698,649 Desolder apparatus
Apparatus and methods for removing solder ball connections from electrical circuits are disclosed. The apparatus and methods comprise a solder ball removing tool...
US-6,698,082 Micro-electromechanical switch fabricated by simultaneous formation of a resistor and bottom electrode
The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical...
US-6,697,982 Generating netlist test vectors by stripping references to a pseudo input
A method for enabling test vectors to be generated for a customer designed integrated circuit having an embedded vendor circuit is disclosed. The embedded vendor...
US-6,697,916 Cache with block prefetch and DMA
A digital system and method of operation is provided in which the digital system has at least one processor, with an associated multi-segment cache memory...
US-6,697,642 Wireless communications apparatus
Apparatus for a wireless communication network, comprises: a directional beam antenna, an antenna controller for directing said directional beam antenna in an...
US-6,697,492 Digital signal processing acoustic speaker system
A technique for realizing high-speed and high-precision acoustic reproduction using acoustic speakers. The audio signal processing system has a sub-band analysis...
US-6,697,416 Digital programmable, spread spectrum clock generator
A digital spread spectrum clock generator. The generator includes a digital waveform generator adapted to generate a sequence of digital words representing a...
US-6,697,184 Method and system for steering a collimated light beam with a pivotable mirror
An optical system 200 includes a light source 202, such as a laser diode. A rotatable mirror 208 is positioned to receive a light beam 220 from the light source...
US-6,697,108 Fast frame readout architecture for array sensors with integrated correlated double sampling system
A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse...
US-6,697,084 Tone display method
A tone display method which prevents degradation in image quality of moving images when the subfield method is utilized without an increase in cost. When tone...
US-6,697,003 System and method for dynamic element matching
Dynamic element matching systems and methods are provided in which a current dynamic element matching code is generated according to a previous dynamic element...
US-6,696,998 Apparatus for generating at least one digital output signal representative of an analog signal
An apparatus for generating a digital signal representative of an analog signal includes two signal conversion devices, each having an analog signal section...
US-6,696,896 Method for implementing high frequency programmable poles and zeros in disk drive preamplifiers
A pole and zero circuit for changing the position of a pole, or a zero, of an amplifier including a capacitor to change the position of the pole or zero for the...
US-6,696,861 Switch mode regulator controller using hybrid technique
A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP...
US-6,696,824 Reduction of external component count in variable voltage integrated DC/DC converter
A variable DC/DC converter system is provided that includes a feedback voltage device and a compensation device. The compensation device and compensation...
US-6,696,757 Contact structure for reliable metallic interconnection
A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is...
US-6,696,644 Polymer-embedded solder bumps for reliable plastic package attachment
A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each...
US-6,696,337 Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral...
In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate...
US-6,696,332 Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a...
US-6,694,467 Low power testing of very large circuits
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-6,694,465 Low overhead input and output boundary scan cells
Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of...
US-6,694,385 Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip....
US-6,694,123 Talking book method and system
A talking book and a method of authoring a talking book is presented where the talking book includes a synthesizer, an audio system, a memory, a display, and...
US-6,694,063 Offset correction of the output of a charge coupled device
An offset is used to correct the output of a charge coupled device (CCD). The correction to the offset is determined by an exponential curve which allows for...
US-6,693,719 Path to trapezoid decomposition of polygons for printing files in a page description language
This invention cures many inefficiencies with known scan conversion methods. This invention employs an edge array rather than a set linked list from an array of...
US-6,693,478 System and method for implementing soft power up
A system and method are disclosed to help protect a node of associated circuitry from overshooting or undershooting, such as can be associated with power up or...
US-6,693,357 Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect...
US-6,693,356 Copper transition layer for improving copper interconnection reliability
The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said...
US-6,692,976 Post-etch cleaning treatment
The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant...
US-6,692,697 Versatile flow cell front-end for optically-based integrated sensors
A versatile flow cell front-end (104) for storing and delivering reagents, test samples, and other transportable materials within an optically-based integrated...
US-6,692,633 Sacrificial anode for corrosion protection of semiconductor metallization during sawing
Resistance to corrosion of aluminum metallization on semiconductor devices during wafer sawing process is provided by a sacrificial anode containing magnesium in...
US-6,692,249 Hot liner insertion/removal fixture
A fixture (30) adapted to permit the heated exchange of a liner (14) from an operating vertical furnace (10). The fixture is adapted to secure to the base of the...
US-6,691,298 Memory management in embedded system with design time object instantiation
A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is...
US-6,691,240 System and method of implementing variabe length delay instructions, which prevents overlapping lifetime...
A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a...
US-6,691,216 Shared program memory for use in multicore DSP devices
A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because...
US-6,691,186 Dual sequencer based disk formatter
The present invention provides for a dual sequencer for use in a peripheral storage device system, as well as a new protocol for data retrieval/storage in...
US-6,691,077 Capture and conversion of mixed-signal test stimuli
A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion...
US-6,690,888 Method for establishing and maintaining optical, open-air communications link
A method for controlling an optical, path-to-sight link, the optical link including a source of light having a beam of light, a controllable beam steering device...
US-6,690,750 Flexible Viterbi decoder for wireless applications
A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric...
US-6,690,668 Modular interconnection of network switches
Network switching systems (10, 110, 210, 310, 410) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices (20)...
US-6,690,259 Security system to enable authenticated access of an individual to a protected area
A security system to enable authenticated access of an individual to a protected area, including a remote control unit (22) with a transponder (28), carried by...
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