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Patent # Description
US-6,690,242 Delay circuit with current steering output symmetry and supply voltage insensitivity
A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal...
US-6,690,228 Bandgap voltage reference insensitive to voltage offset
A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has...
US-6,690,147 LDO voltage regulator having efficient current frequency compensation
A low drop out linear voltage regulator (200) overcomes the dynamic quiescent current limitation by creating an internal zero that moves in the same direction...
US-6,690,066 Minimization and linearization of ESD parasitic capacitance in integrated circuits
An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive...
US-6,689,686 System and method for electroplating fine geometries
An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is...
US-6,689,678 Process for fabricating ball grid array package for enhanced stress tolerance
The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like...
US-6,689,634 Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or...
A modeling technique for selectively depopulating solder balls (12) (and their respective solder ball pads (34), vias (32) and traces or lines (30)) from a...
US-6,688,453 Railing for a boat conveyor system
A conveyor system (30) comprises: a boat (20), a feed belt (36), a feed pulley (38), and improved railings (34). The boat (20) is adapted to carry a component or...
US-6,687,973 Optimized metal fuse process
A metal fuse process that uses a thinner (e.g., 6000 .ANG.) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for...
US-6,687,796 Multi-channel DMA with request scheduling
A digital system is provided with a multi-channel DMA controller (400) for transferring data between various resources (401, 402). Each channel includes a source...
US-6,687,779 Method and apparatus for transmitting control information across a serialized bus interface
A bus interface device includes a parallel input configured to be coupled to a bus (20), such as a primary PCI bus. The device also includes a parallel data...
US-6,687,777 Apparatus and method of connecting and interfacing active device components
A method and apparatus of connecting an active computing device (15) to an active peripheral option (20) comprising the steps of making a physical connection...
US-6,687,775 Dual purpose serial/parallel data transfer device for peripheral storage device
A peripheral storage device system and a data transfer device for use in a peripheral storage device system are disclosed, which provide for selective...
US-6,687,769 Serial peripheral interface with high performance buffering scheme
The serial peripheral interface and high performance buffering scheme according to the present invention addresses many of the shortcomings of the prior art. In...
US-6,687,642 Condition responsive sense system and method
An application specific integrated circuit or ASIC (MSC) is connected to a plurality of bridge type sense elements (1-6) for analog multiplexing (10a, 10b, 10c)...
US-6,687,489 Implementing RF power measurements in a broadband communications device
The invention provides systems, methods, and devices that compensate for temperature, frequency, and sampling effects in a broadband communication device's power...
US-6,687,412 Method and system for generating image compression quantization matrices
A system (100) for generating image compression matrices is disclosed. The present invention includes an image (102) having pixel block arrays (104). The present...
US-6,687,376 High-speed long code generation with arbitrary delay
A circuit is designed with a first register circuit (364) arranged to store a state matrix. A memory circuit (710) is arranged to store a plurality of ...
US-6,687,292 Timing phase acquisition method and device for telecommunications systems
A timing phase acquisition method and device for burst modems includes an receiver designed to initialize an equalizer filter by matching clock of the equalizer...
US-6,687,145 Static random access memory cell and method
A method for forming a scaled static random access memory (SRAM) cell (10) based on an initial SRAM cell for implementation in a technology scaled from an...
US-6,687,132 Conductive member grid array interface for mirror array drive apparatus
The present invention discloses drive apparatus for rotating a mirror used for switching light signals. The drive apparatus has reduced internal wiring and uses...
US-6,687,064 Write head fault detection circuit and method
A circuit (30, 40) and method for detecting faults of a write head (18) of a hard-disk drive system (70). A first resistor R.sub.1 and a second resistor R.sub.2...
US-6,686,773 Reducing short circuit power in CMOS inverter circuits
A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback...
US-6,686,729 DC/DC switching regulator having reduced switching loss
A DC/DC switching regulator has a semiconductor switch coupled to an inductor, a first capacitor and a rectifier. A circuit to improve the switching efficiency...
US-6,686,300 Sub-critical-dimension integrated circuit features
A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a...
US-6,686,291 Undercut process with isotropic plasma etching at package level
A method (30) of fabricating a micromechanical device (10) by performing spacer layer undercutting (46) and passivation at the package level. A back-end assembly...
US-6,686,283 Shallow trench isolation planarization using self aligned isotropic etch
A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed...
US-6,686,237 High precision integrated circuit capacitors
A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer...
US-6,686,236 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other...
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of...
US-6,686,225 Method of separating semiconductor dies from a wafer
Methods are disclosed for manufacturing semiconductor device dies and for separating dies from a semiconductor wafer, wherein one or more channels are etched in...
US-6,686,210 Methods for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization...
A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment...
US-6,686,102 Two-exposure phase shift photolithography with improved inter-feature separation
A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same...
US-6,685,073 Method and apparatus for stretching and processing saw film tape after breaking a partially sawn wafer
A method and apparatus for separating a wafer into wafer portions comprising a larger wafer flex-frame (50) supported on a support base (40) and a smaller...
US-6,684,283 Method for interfacing a cardbay card to the host system by indicating a 16-bit or cardbus PC card insertion to...
The present invention provides a method, system and apparatus of interfacing a CardBay device (520) using existing Card and Socket Services (CSS) software (530)....
US-6,684,280 Task based priority arbitration
A digital system and method of operation is provided in which several processors (1400, 1402, 1404) are connected to a shared resource (1432). Each processor has...
US-6,684,125 In-situ randomization and recording of wafer processing order at process tools
Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing...
US-6,683,625 System and method for advanced interfaces for virtual environments
A system and method for providing a controllable virtual environment includes a computer (11) with processor and a display coupled to the processor to display...
US-6,683,443 Soft start circuit for regulated power supply
A power supply feedback circuit includes a regulating element at an input side of an optical isolator. The control lead for the regulating element is connected...
US-6,683,380 Integrated circuit with bonding layer over active circuitry
An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E)....
US-6,683,371 Methods of and apparatus for manufacturing ball grid array semiconductor device packages
A method of manufacturing a ball grid array semiconductor package includes the step of providing a substrate (103) having a first surface (103b) and a second...
US-6,683,290 Constant light disable for spatial light modulator
A method and system of detecting whether the intensity of light incident a spatial light modulator varies periodically. One embodiment provides a method of...
US-6,682,994 Methods for transistor gate formation using gate sidewall implantation
Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are...
US-6,682,980 Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion...
US-6,682,635 Cathodic sputtering chamber for applying material to the surface of a semiconductor wafer located therein
A chamber (10) for applying material to the surface of a semiconductor wafer (18) located in the chamber by means of cathodic sputtering a target (26), located...
US-6,681,319 Dual access instruction and compound memory access instruction with compatible address fields
A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured...
US-6,681,297 Software controlled cache configuration based on average miss rate
A digital system is provided with a several processors (1302), a shared level two (L2) cache (1300) having several segments per entry with associated tags, and a...
US-6,681,270 Effective channel priority processing for transfer controller with hub and ports
A data transfer controller with hub and ports uses an effective channel priority processing technique and algorithm. Data transfer requests are queued in a...
US-6,680,504 Method for constructing a metal oxide semiconductor field effect transistor
A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region...
US-6,680,484 Space efficient interconnect test multi-structure
The present invention relates to a test structure and a method for forming a test structure over a semiconductor substrate. The test structure comprises a...
US-6,680,249 Si-rich surface layer capped diffusion barriers
A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is...
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