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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-9,813,072 |
Methods and apparatus to increase an integrity of mismatch corrections of
an interleaved analog to digital... Methods, apparatus, systems and articles of manufacture to increase an integrity of mismatch corrections in an interleaved analog to digital converter are... |
| US-9,813,065 |
Simultaneous LVDS I/O signaling method and apparatus First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an... |
| US-9,813,053 |
Gate capacitance control in a load switch A switch for controlling a power supply and a method of operating the switch are disclosed. The switch includes a first transistor having a drain and a source... |
| US-9,813,040 |
Resistor attenuator with switch distortion cancellation A programmable (multistep) resistor attenuator architecture (such as for input to a differential amplifier) provides cancellation for harmonic distortion... |
| US-9,813,005 |
Stator resistance estimation for electric motors A method of controlling an electric motor (motor) includes providing a processor having an associated memory storing a stator resistance (Rs) estimation (RSE)... |
| US-9,812,960 |
Methods and apparatus for a low standby current DC-DC power controller
with improved transient response Methods and apparatus for DC-DC power controller with low standby current and fast transient response. In an example arrangement, an apparatus includes a... |
| US-9,812,452 |
Method to form silicide and contact at embedded epitaxial facet An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an... |
| US-9,812,439 |
Bi-directional ESD protection circuit An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated... |
| US-9,812,384 |
Semiconductor device having compliant and crack-arresting interconnect
structure A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first... |
| US-9,812,115 |
Active noise-cancellation feedback signal transmission A noise-cancelling system includes headset for generating a feedback signal for noise-cancellation in response to sound externally generated from the headset.... |
| US-9,811,925 |
Method and apparatus to render lines on a display screen Disclosed examples include drawing apparatus and methods of rendering lines on a display screen, in which a first angle is determined that corresponds to a hand... |
| US-9,811,917 |
Confidence estimation for optical flow under low light conditions A confidence map for optical flow gradients is constructed calculating a set of census texture gradients for each pixel of an image, filtering said gradients... |
| US-9,811,688 |
Authentication with battery and host programmed with shared identity key Systems and methods for providing a battery module 110 with secure identity information and authentication of the identity of the battery 110 by a host 120. In... |
| US-9,811,619 |
Low drop-out voltage regulator modeling systems and methods A specialized low drop-out voltage regulator (LDO) computer system stores a generalized base model of an LDO. The base model includes values representing a... |
| US-9,811,607 |
System and method to extract unique elements from sorted list A device includes an input array register, a determining component and a computing component. The input array register stores a sorted list of n elements as an... |
| US-9,811,483 |
Configurable serial communication hub An apparatus and method for configuring a serial communication hub are disclosed herein. A serial communication hub includes an upstream port, a plurality of... |
| US-9,811,229 |
Capacitive touch sensing A touch sensor apparatus includes a grid of intersecting sensor lines, a plurality of input/output (IO) pins, a plurality of diodes, a processor coupled to the... |
| US-9,811,148 |
Static power reduction in caches using deterministic naps The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional... |
| US-9,811,136 |
Charging a provider/consumer with a dead battery via USB power delivery A VBUS conductor is checked to determine whether a voltage on the VBUS conductor is greater than a vSafe0V voltage within a detect time interval. A device... |
| US-9,811,112 |
Adaptive clock delay compensation A system includes a CPU, a serial interface, and an adaptive clock delay compensator. The adaptive clock delay compensator is configured to generate a clock... |
| US-9,811,104 |
Reference voltage generator system for reducing noise One example includes an reference voltage generator system. The system includes an amplifier configured to generate a reference voltage based on a respective... |
| US-9,808,163 |
Method and apparatus for heart rate monitoring A method and apparatus for monitoring heart rate. The method includes receiving a digital heart monitoring signal, determining the integrity of said signal with... |
| US-9,806,735 |
High speed data transfer for analog-to-digital converters This disclosure describes techniques for transferring data from an analog-to-digital converter (ADC) to a host device. The techniques may determine whether an... |
| US-9,806,730 |
Apparatus having source follower based DAC inter-symbol interference
cancellation A current digital-to-analog converter (DAC) and an integrated circuit chip including the DAC are disclosed. The current DAC includes a switching circuit that... |
| US-9,806,673 |
Class-E outphasing power amplifier with efficiency and output power
enhancement circuits and method An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF... |
| US-9,806,619 |
Time-interleaved current feedback droop function for multiphase buck
converters Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a... |
| US-9,806,614 |
Low power zero inductor current detection circuit Methods and apparatus for detecting a zero inductor current to control switch transitions for a power converter. An example method includes outputting a first... |
| US-9,806,610 |
Noise-shaped power converters Noise-shaped frequency hopping power converters are disclosed. An example noise-shaped frequency hopping power converter comprises a shaped number generator... |
| US-9,806,607 |
Circuit for controlling a power supply voltage for a high-side gate driver This disclosure describes techniques for controlling a power supply voltage for a high-side gate driver that is used in a power converter. In some examples, in... |
| US-9,806,547 |
Circuits, devices, methods and systems to secure power-up for battery
operating devices even with low current... An electronic power control circuit includes a power conditioner circuit (120, 130) having a charging input line (116), a battery-related line (133) of the... |
| US-9,806,148 |
Device isolator with reduced parasitic capacitance Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel... |
| US-9,806,074 |
High voltage multiple channel LDMOS An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a... |
| US-9,805,986 |
High mobility transistors An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have... |
| US-9,805,788 |
Array power supply-based screening of static random access memory cells
for bias temperature instability A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory... |
| US-9,800,272 |
Circuits and methods for transmitting signals For generating quantized signals, a quantized phase domain related to quantized phases of an input signal is generated. Vectors that the input signal may occupy... |
| US-9,800,235 |
Adaptive edge-rate boosting driver with programmable strength for signal
conditioning A signal conditioner that includes a transition-detection module and a current-injection module. The transition-detection module is configured to receive a pair... |
| US-9,800,191 |
Adaptive linear resonance actuator controller A system includes a controller to control movement of a linear resonant actuator (LRA). The system includes a monitor in the controller to monitor a back... |
| US-9,799,408 |
Memory circuit with leakage compensation A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the... |
| US-9,799,395 |
Sense amplifier in low power and high performance SRAM A static random access memory (SRAM) includes an array of storage cells and a first sense amplifier. The array of storage cells is arranged as rows and columns.... |
| US-9,799,389 |
Circuit and method for imprint reduction in FRAM memories A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B.sub.0, B.sub.1). A... |
| US-9,797,748 |
Gear sensing based on differential/asymmetric inductive sensing An inductive gear sensing system suitable for sensing gear (gear tooth) movement, such as some combination of speed, direction and position, based on... |
| US-9,794,955 |
Configuration of CSI-RS for CoMP feedback This invention is a manner of Coordinated Multi-Point (CoMP) transmission between with plural base stations and at least one user equipment. The user equipment... |
| US-9,794,560 |
Method and system for video picture intra-prediction estimation Several systems and methods for intra-prediction estimation of video pictures are disclosed. In an embodiment, the method includes accessing four `N.times.N`... |
| US-9,793,923 |
LDPC post-processor architecture and method for low error floor conditions Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving... |
| US-9,793,918 |
Memory compression operable for non-contiguous write/read addresses A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality... |
| US-9,793,882 |
Voltage clamp circuit One example includes a voltage clamp circuit. The voltage clamp circuit includes a comparator loop circuit. The comparator loop circuit includes a comparator... |
| US-9,793,707 |
Fast transient precision power regulation apparatus Apparatus disclosed herein implement a fast transient precision current limiter such as may be included in an electronic voltage regulator. The current limiter... |
| US-9,793,375 |
High voltage lateral DMOS transistor with optimized source-side blocking
capability An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an... |
| US-9,793,364 |
Substrate contact having substantially straight sidewalls to a top surface
of the substrate A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step... |
| US-9,793,214 |
Heterostructure interconnects for high frequency applications An integrated circuit includes an interconnect which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the... |
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