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Self-initialized soft start for Miller compensated regulators
A Miller compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage...
Low ripple scalable DC-to-DC converter circuit
A circuit for boosting an input voltage (V.sub.IN) to provide a low ripple output voltage (V.sub.OUT) regulates flow of current between a source of the input...
Circuit assembly for doubling the voltage of a battery
A circuit assembly for doubling the voltage of a battery includes a charge pump (12) fed by the battery voltage and controlled by a clock generator (10). The...
Integrated charge and voltage mode drive circuit for piezo actuators used
in mass data storage devices, or the like
A driver (40) for supplying drive signals to a piezo element (48) of a milli-actuator device (21) in a mass data storage device (10) in a charge mode of...
Analog pre-processor with improved input common mode range
An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first...
Method for forming a metal extrusion free via
A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process...
Reduction in well implant channeling and resulting latchup characteristics
in shallow trench isolation by...
Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of...
Method for forming a memory integrated circuit
A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region...
High capacitance damascene capacitors
The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75...
Test system for ferroelectric materials and noble metal electrodes in
A method is provided for ferroelectric layer testing. An adhesion layer is deposited over a semiconductor substrate to be of a phase pure material lacking a...
Method to achieve continuous hydrogen saturation in sparingly used
electroless nickel plating process
An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In...
Current controlled multi-state parallel test for semiconductor device
A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and...
Content-based video compression
A video compression method and system including object-oriented compression plus error correction using decoder feedback.
Method and system for configuring integrated systems on a chip
A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method...
Surface micro-planarization for enhanced optical efficiency and pixel
performance in SLM devices
A method for enhancing the optical performance of a reflective spatial light modulator by micro-planarizing surfaces within the SLM, such as the reflective...
Telescopic reconstruction of facial features from a speech pattern
To reduce the needed bandwidth of video communication system, a portion of the video image that differs from a preceding frame of the video image is predicted...
Precise differential voltage interpolation analog-to-digital converter
having double interpolation using...
A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion...
Sigma-delta analog-to-digital converter having improved reference
A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The...
Zero-overhead class G amplifier with threshold detection
The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply...
Method and circuit for trimming offset and temperature drift for
operational amplifiers and voltage references
A trimming circuit and method of trimming is provided for offset and temperature drift trimming of an op amp or voltage reference device, having an input stage,...
Modulation scheme for filterless switching amplifiers with reduced EMI
A ternary modulation scheme for filterless switching amplifiers with reduced EMI reduces the common mode component of the signal by allowing only one state with...
A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29....
Ultra-fast voltage drive
An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N.sub.1). A pair of bipolar output transistors (Q.sub.3, Q.sub.4) are...
Failsafe interface circuit with extended drain devices
Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad...
Digital method of measuring driver slew rates for reduced test time
A circuit combination (16,86) is presented for providing digital signals indicative of slew rates of drive signals (112,140) provided to H-bridge power drive...
Socket apparatus and method for removably mounting an electronic package
A socket (10) has a plurality of contacts (13) arranged in base (11). Each contact has one arm (13a) for contacting a solder ball of an electronic package (2). A...
Method for spin coating high viscosity materials on silicon wafers
A method for spin coating high viscosity materials. Two dispense steps are used. The first dispense step dispenses a small amount (102) of high viscosity...
Lower temperature method for forming high quality silicon-nitrogen
A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick...
Boundary scan test cell circuit
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for...
Method and system for reducing power in a parallel-architecture multiplier
A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch...
Method and apparatus for combining memory blocks for in circuit emulation
An emulation device is provided that has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory within the emulation...
Asynchronous FIFO memory having built-in self test logic
An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency...
Memory array and wordline driver supply voltage differential in standby
An SRAM array 22, with improved leakage in standby, raises the wordline driver lower supply voltage Vss-WL when raising the array lower supply voltage Vss-array...
Multi-bit sigma-delta modulator employing dynamic element matching using
adaptively randomized data-weighted...
A sigma-delta modulator disclosed herein provides a first order noise shaping of the errors associated with the multi bit DAC employing unit elements, without...
Method and apparatus for two zeros/two poles active compensation phase
A phase locked loop with two zeros/two poles active compensation. The two poles and two zeros provide increased stability with capability for narrow bandwidth...
Switched capacitor scheme for offset compensated comparators
An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage...
Internally and externally biased dual mode 1394 compliant driver
A dual mode output driver circuit within the architecture of a IEEE 1394-1995 IEEE 1394b compliant physical layer (PHY) circuit address the deficiencies of...
Method for uniform nitridization of ultra-thin silicon dioxide layers in
A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing...
Multi-channel serial port with programmable features
A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry...
Microphone bias current measurement circuit
A microphone bias current detection circuit includes: a microphone circuit 18; an amplifier 10 having a first output and a second output, the first output is...
Coding method for video signal based on the correlation between the edge
direction and the distribution of the...
The objective of the invention is to make high-efficiency compressed coding for images. In coding of video signals in this application example, the edge is...
Method for collision avoidance in an asynchronous communication system
A method of avoiding collisions among a plurality of transmitters that communicate asynchronously in relation to each other with a single receiver. The...
Method and apparatus for storing data in an integrated circuit
A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the...
Pulse width modulation regulator control circuit having precise frequency
and amplitude control
A control circuit (50) for a switch mode power converter having precise control of amplitude and frequency that does not exhibit overshoot error nor undershoot...
To provide a regulator circuit capable of preventing oscillation of output voltage when an overcurrent regulating function is activated voltage across resistor...
Gate stack and etch process
A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks...
Optimized hardware cleaning function for VIVT data cache
A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX...
Unified memory system architecture including cache and directly addressable
static random access memory
A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is...
Emulation system with address comparison unit and data comparison unit
In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation...
Feedback control for hybrid compression
A closed loop feedback system adaptively controls the compression ratio in a Raster Image Processor. The image content is analyzed in real time, and rasterized...