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Patent # Description
US-6,618,186 Micro-electromechanical system
To suppress undesired scattered light and leaking light so as to improve the optical function and reliability. In this DMD, as the address circuit of one cell,...
US-6,618,083 Mismatch-independent reset sensing for CMOS area array sensors
Two methods for suppressing the fixed pattern noise effects of a pixel reset switch by ensuring that the reset NMOS device operates in its linear region. The...
US-6,617,989 Resistor string DAC with current source LSBs
A method and apparatus for converting an N-bit digital word to an analog voltage signal. A first circuit converts the MSBs of the N-bit word and a second circuit...
US-6,617,921 High output swing comparator stage
A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate...
US-6,617,906 Low-current compliance stack using nondeterministically biased Zener strings
Systems and methods are provided for limiting voltage to low-voltage devices employing a high-voltage supply. The systems and methods employ voltage limiting...
US-6,617,886 Differential pair with high output signal crossover
A buffer circuit includes a differential pair output switch having an additional NPN device and resistor operational to increase the common mode output voltage...
US-6,617,872 Reduced cost, high speed integrated circuit test arrangement
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate...
US-6,617,846 Method and system for isolated coupling
A method for isolatively coupling an input signal to an output signal, where the input signal is a first voltage differential, comprises three steps. Step one...
US-6,617,844 Compare path bandwith control for high performance automatic test systems
The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for...
US-6,617,835 MOS type reference voltage generator having improved startup capabilities
A reference voltage generator having high-speed starting at a low power source voltage and with high stability and high precision, without substantially...
US-6,617,834 Switched power supply with voltage regulator having PWM with hysteretic loop controller and method for...
A switched power supply (40) has a pulse width modulator to adjust a pulse width that controls the output voltage (104). The width modulator includes a...
US-6,617,833 Self-initialized soft start for Miller compensated regulators
A Miller compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage...
US-6,617,832 Low ripple scalable DC-to-DC converter circuit
A circuit for boosting an input voltage (V.sub.IN) to provide a low ripple output voltage (V.sub.OUT) regulates flow of current between a source of the input...
US-6,617,828 Circuit assembly for doubling the voltage of a battery
A circuit assembly for doubling the voltage of a battery includes a charge pump (12) fed by the battery voltage and controlled by a clock generator (10). The...
US-6,617,758 Integrated charge and voltage mode drive circuit for piezo actuators used in mass data storage devices, or the like
A driver (40) for supplying drive signals to a piezo element (48) of a milli-actuator device (21) in a mass data storage device (10) in a charge mode of...
US-6,617,567 Analog pre-processor with improved input common mode range
An analog circuit 20 includes an amplifier 30 with a positive input node, a negative input node, a positive output node and a negative output node. A first...
US-6,617,231 Method for forming a metal extrusion free via
A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process...
US-6,617,217 Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by...
Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of...
US-6,617,211 Method for forming a memory integrated circuit
A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region...
US-6,617,208 High capacitance damascene capacitors
The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75...
US-6,617,178 Test system for ferroelectric materials and noble metal electrodes in semiconductor capacitors
A method is provided for ferroelectric layer testing. An adhesion layer is deposited over a semiconductor substrate to be of a phase pure material lacking a...
US-6,616,967 Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process
An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In...
US-6,615,391 Current controlled multi-state parallel test for semiconductor device
A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and...
US-6,614,847 Content-based video compression
A video compression method and system including object-oriented compression plus error correction using decoder feedback.
US-6,614,703 Method and system for configuring integrated systems on a chip
A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method...
US-6,614,576 Surface micro-planarization for enhanced optical efficiency and pixel performance in SLM devices
A method for enhancing the optical performance of a reflective spatial light modulator by micro-planarizing surfaces within the SLM, such as the reflective...
US-6,614,466 Telescopic reconstruction of facial features from a speech pattern
To reduce the needed bandwidth of video communication system, a portion of the video image that differs from a preceding frame of the video image is predicted...
US-6,614,379 Precise differential voltage interpolation analog-to-digital converter having double interpolation using...
A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion...
US-6,614,375 Sigma-delta analog-to-digital converter having improved reference multiplexer
A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The...
US-6,614,310 Zero-overhead class G amplifier with threshold detection
The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply...
US-6,614,305 Method and circuit for trimming offset and temperature drift for operational amplifiers and voltage references
A trimming circuit and method of trimming is provided for offset and temperature drift trimming of an op amp or voltage reference device, having an input stage,...
US-6,614,297 Modulation scheme for filterless switching amplifiers with reduced EMI
A ternary modulation scheme for filterless switching amplifiers with reduced EMI reduces the common mode component of the signal by allowing only one state with...
US-6,614,276 Flip-flop design
A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29....
US-6,614,273 Ultra-fast voltage drive
An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N.sub.1). A pair of bipolar output transistors (Q.sub.3, Q.sub.4) are...
US-6,614,262 Failsafe interface circuit with extended drain devices
Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad...
US-6,614,255 Digital method of measuring driver slew rates for reduced test time
A circuit combination (16,86) is presented for providing digital signals indicative of slew rates of drive signals (112,140) provided to H-bridge power drive...
US-6,614,247 Socket apparatus and method for removably mounting an electronic package
A socket (10) has a plurality of contacts (13) arranged in base (11). Each contact has one arm (13a) for contacting a solder ball of an electronic package (2). A...
US-6,613,700 Method for spin coating high viscosity materials on silicon wafers
A method for spin coating high viscosity materials. Two dispense steps are used. The first dispense step dispenses a small amount (102) of high viscosity...
US-6,613,698 Lower temperature method for forming high quality silicon-nitrogen dielectrics
A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick...
US-6,611,934 Boundary scan test cell circuit
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for...
US-6,611,857 Method and system for reducing power in a parallel-architecture multiplier
A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch...
US-6,611,796 Method and apparatus for combining memory blocks for in circuit emulation
An emulation device is provided that has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory within the emulation...
US-6,611,469 Asynchronous FIFO memory having built-in self test logic
An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency...
US-6,611,451 Memory array and wordline driver supply voltage differential in standby
An SRAM array 22, with improved leakage in standby, raises the wordline driver lower supply voltage Vss-WL when raising the array lower supply voltage Vss-array...
US-6,611,221 Multi-bit sigma-delta modulator employing dynamic element matching using adaptively randomized data-weighted...
A sigma-delta modulator disclosed herein provides a first order noise shaping of the errors associated with the multi bit DAC employing unit elements, without...
US-6,611,176 Method and apparatus for two zeros/two poles active compensation phase locked loops
A phase locked loop with two zeros/two poles active compensation. The two poles and two zeros provide increased stability with capability for narrow bandwidth...
US-6,611,163 Switched capacitor scheme for offset compensated comparators
An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage...
US-6,611,155 Internally and externally biased dual mode 1394 compliant driver
A dual mode output driver circuit within the architecture of a IEEE 1394-1995 IEEE 1394b compliant physical layer (PHY) circuit address the deficiencies of...
US-6,610,614 Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing...
US-6,609,163 Multi-channel serial port with programmable features
A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry...
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