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Compensation circuit for fractional-N frequency PLL synthesizer
Frequency synthesizer (1) has compensation circuit (45) and correction circuit (10). Compensation circuit (45) has compensation capacitor (46), while correction...
Power saving circuitry using predictive logic
To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12)...
Lightly donor doped electrodes for high-dielectric-constant materials
A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a ...
Memory cell with reduced coupling between pass transistor and drive
transistor bodies and method
According to one embodiment of the present invention, a semiconductor structure includes an SOI memory cell having a pass transistor having a body and a driver...
Attenuated rim phase shift mask
An embodiment of the instant invention is a mask having a pattern which is transferred to a layer overlying a semiconductor wafer, the mask comprising: a...
Chemical solution and method for reducing the metal contamination on the
surface of a semiconductor substrate
The present invention is related to a method for reducing the metal contamination on a surface of a semiconductor substrate wherein said substrate is submitted...
Measuring integrated circuit layout efficiency
A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C...
CRC-based adaptive halting turbo decoder and method of use
A CRC-based adaptive halting turbo decoder applies a CRC code to identify internally generated information sequences. The information sequences are encoded with...
Coprocessor for synthesizing signals based upon quadratic polynomial
A coprocessor (15) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system (20) having a host processor (12) that forwards...
Pseudo arbitrary waveform generator
A method of waveform generation using a VLSI digital tester unit without an arbitrary waveform generator. A software application produces a series of vectors to...
Illumination system for scrolling color recycling
Distortion optics are used to efficiently couple a spiral color wheel and an orthogonal modulator. Light 602 from a light source enters an aperture in a...
Method and apparatus providing spatial diversity within an indoor network
A method and architecture that provides network level spatial diversity using multiple indoor access points (70) has a transceiver coupled to each wireless...
DVD radial runout cancellation with self-calibration
A self-calibrating radial runout cancellation method for DVD optical disc media. The radial runout of an optical disc is first measured, during closed-loop...
On-chip charge distribution measurement circuit
A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A...
Apparatus and methods for imprint reduction for ferroelectric memory cell
Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory...
Analog pulse width modulation of video data
A micromirror capable of analog pulse width modulation, and method thereof A capacitor (406) in each micromirror element stores a charge representative of one...
Data acquisition system using predictive conversion
A data acquisition system uses an analog-to-digital converter (ADC) that includes a prediction feedback element. Using the computing power of a digital signal...
Clock generator circuit with a PLL having an output frequency cycled in a
range to reduce unwanted radiation
A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL...
Operational amplifier topology and method
A technique is disclosed which facilitates the layout of op amp cells, for example, two-stage op amp cells or three-stage op amp cells, to provide larger...
System and method of translating wide common mode voltage ranges into
narrow common mode voltage ranges
A system and method is provided for translating a wide common mode voltage range into a narrow common mode voltage range. The system and method extend the common...
Maintaining substantially constant trans-conductance without substantially
changing power consumption
The current passing in a main trans-conductor circuit is compared in analog domain with a reference current. If the passing current exceeds the reference...
Die testing using top surface test pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...
Low pressure, low temperature, semiconductor gap filling process
A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures...
Method of estimation of wafer-to-wafer thickness
A method for extracting wafer-to-wafer thickness variation from interferometry signals off patterned (product) wafer polish during non-endpointed CMP. The method...
Multi-sensor assisted cellular handoff technique
A system and method for assisting in handoff in a cellular communication system. The system includes a base station having a data base of patterns of known...
Phase detector architecture for phase error estimating and zero phase
A system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks...
Apparatus and method for refreshing a flash memory unit
In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that...
Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device...
Capacitor bias recovery methodology
A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier...
Projector for digital cinema
A digital cinema projection system (200) for projecting images onto a display screen. The projection system (200) comprises a lamp console (102) and a projector...
Flexible interface circuit and method for delta sigma A/D converters
A multi-mode interface circuit for coupling a delta sigma modulator (24) to a processor includes a decoder 20 for decoding mode selection inputs to produce a...
Methods and apparatus for trimming packaged electrical devices
An electrical device is disclosed, comprising electrical components forming an electrical circuit, with a trim circuit comprising two or more trim cells...
Approach to structurally reinforcing the mechanical performance of silicon
level interconnect layers
A conductive via pattern (110) between the uppermost metal interconnect layer (M.sub.n) and next underlying metal interconnect layer (M.sub.n-1) in the bond pad...
Plastic chip-scale package having integrated passive components
A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic...
Reducing copper line resistivity by smoothing trench and via sidewalls
A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106)....
Whole wafer MEMS release process
A process for manufacturing a wafer having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. The devices on the wafer...
Transient fuse for charge-induced damage detection
A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the...
System signalling schemes for processor & memory module
A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and...
Bus transaction accelerator for multi-clock systems
A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different...
Apparatus and method for address modification in a direct memory access
In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory...
Method and system for dispatching semiconductor lots to manufacturing
equipment for fabrication
A method for dispatching available lots to unallocated machines is provided that includes receiving metrics data (26) providing performance measurements for a...
Method of providing read bias during servo block write
The manufacturer of hard disk drives (HDD) simultaneously activates all write heads to format the magnetoresistive disks during an operation known in the...
Micromechanical device and method for non-contacting edge-coupled operation
A new non-contacting, edge-coupled micromechanical device and method, requiring no contact between the mirror or underlying yoke and landing pads on the...
Correction circuit for beta mismatch between thermometer encoded and R-2R
ladder segments of a current steering DAC
A current correction circuit 500 eliminates beta mismatches between a thermometer encoded segment 102 and a R-2R ladder segment 106 of a current steering...
Reduced cost, high speed circuit test arrangement
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate...
Ball grid array package for enhanced stress tolerance
The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like...
Thin tin preplated semiconductor leadframes
A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of...
Semiconductor device and its manufacturing method
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is...
Extended life source arc chamber liners
A liner (102) for an arc chamber (100) of an ion implanter. The arc chamber (100) comprises a liner (102) on the inner surface (104) of the arc chamber (100)...
Solid hermetic via and bump fabrication
A method of forming an electrically conductive via with bumps on both sides of a substrate wherein there is provided a substrate having a pair of opposing...