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Patent # Description
US-6,642,752 Broadband sample and hold circuit
A sample and hold device is provided in which sample switches are employed to switch between a sample phase and a hold phase. The sample and hold device provides...
US-6,642,737 METHOD OF GENERATING TRANSISTOR AC SCATTERING PARAMETERS SIMULTANEOUSLY WITH DC CHARACTERISTICS USING A SINGLE...
A method of generating transistor scattering parameters employs a single circuit simulation with a self-correction scheme for the artificial DC voltage dropped...
US-6,642,711 Digital inductive position sensor
A differential pulse transformer having a drive coil (10a) and differential sense coils (10b) are disposed on a planar surface with a target (10e, 10f) movable...
US-6,642,696 DC-DC converter with a feedback controller
A DC-DC converter that does not need a series resistance element on the output side, and can make use of the parasitic resistance of a coil to improve output...
US-6,642,601 Low current substantially silicide fuse for integrated circuits
A fuse (50, 150, 200) with a low fusing current includes a first contact element (51, 151, 201) and a second contact element (51, 151, 201). A fusing element...
US-6,642,593 Microelectromechanical switch
A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the...
US-6,642,518 Assembly and method for improved scanning electron microscope analysis of semiconductor devices
An assembly and method for improved scanning electron microscope analysis of semiconductor devices include a structure including a first layer and a second...
US-6,642,503 Time domain sensing technique and system architecture for image sensor
A photodiode sensor (25) has a photodiode (30) with an associated capacitance (34), which may be a parasitic capacitance of the photodiode (30). A switch (36) is...
US-6,642,094 Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide
A method of forming a first and second transistor. The method provides a semiconductor surface (20). Th method also forms a gate dielectric (30) adjacent the...
US-6,641,867 Methods for chemical vapor deposition of tungsten on silicon or dielectric
In situ nitridation of a thin layer of either silicon or tungsten provides an adhesive layer for bulk deposition of tungsten. Alternatively, a thin layer of...
US-6,640,193 Method and system for measuring jitter
According to one embodiment of the present invention, a system (100) for measuring overall jitter is disclosed that includes a data converter (102) that measures...
US-6,639,911 Data communications system with splitterless operation
A data communication system that provides different types of service (e.g., telephone services and high-speed data transmission services) to a remote site even...
US-6,639,826 Memory cell operation using ramped wordlines
The standby power consumption of storage or memory cells is improved by ramping the wordline voltage down at a rate slow enough to allow the addressed storage...
US-6,639,773 Current limiter
A current limiting circuit to limit current including an input circuit to input an input voltage, a connecting circuit to connect the input voltage to a current,...
US-6,639,711 Packaged micromirror assembly with in-package mirror position passive component feedback
A packaged micromirror assembly (21, 21') is disclosed. The assembly (21, 21') includes a mirror element (41) having a mirror surface (29) that can rotate in two...
US-6,639,475 PLL circuit
A circuit for removing a spurious component contained in the output signal in the locked state of a PLL circuit in a fractional frequency division system. For...
US-6,639,460 Residual offset correction method and circuit for chopper stabilized amplifiers
An improved circuit and technique are provided that facilitate residual offset correction during chopper stabilization of an amplifier circuit. A chopper...
US-6,639,395 Current sensor with input/output isolation
A current sensor and a method for measuring currents on an integrated circuit in an isolated manner. The current sensor uses a Peltier device as a thermal...
US-6,639,390 Protection circuit for miller compensated voltage regulators
A capacitively compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage...
US-6,639,373 Driver circuit for a voice coil motor in a disk drive system
The present invention provides an apparatus and system (300) supplying a regulated voltage of sufficient magnitude to enable de-latching of a head carriage from...
US-6,639,367 Control circuit employing preconditioned feedback amplifier for initializing VCO operating frequency
A control circuit for a piezo transformer based power supply includes oscillator circuitry, drive circuitry, sense circuitry, and feedback circuitry collectively...
US-6,639,284 Compensated-well electrostatic discharge protection structure
Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor...
US-6,638,877 Ultra-thin SiO2using N2O as the oxidant
N.sub.2 O is used as the oxidant for forming an ultra-thin oxide (14). The low oxidation efficiency of N.sub.2 O compared to O.sub.2 allows the oxidation...
US-6,638,818 Method of fabricating a dynamic random access memory with increased capacitance
A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are...
US-6,637,894 High contrast projection
A method and system for improving the contrast ratio of a projected image. An asymmetric aperture stop within a lens is used to provide a 20-30% improvement in...
US-6,636,907 Transferring data between asynchronous devices
A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are...
US-6,636,832 Method and system for decoding a compressed data file
A data file having a plurality of frames is received, with each frame having a syncword located at a first predefined length from a known data value that is...
US-6,636,572 High-speed digital timing and gain gradient circuit employing a parallel architecture
A system and a method for implementing a feedback control signal by employing parallel paths (105 and 106) for processing separate parts of the signal. The...
US-6,636,571 Automatic frequency control system with improved argument approximation
An argument approximation method is used to estimate the frequency offset for an automatic frequency control (AFC) circuit. An angle of rotation can be...
US-6,636,560 Increased bit rate of telephony modems using controlled intersymbol interface
The operation of a line card in the local exchange of a point-to-point switched telephone network is modified to increase the data rate of voiceband modem...
US-6,636,553 Pseudorandom noise generator for WCDMA
A circuit is designed with a plurality of logic circuits (370-374) for producing an offset state matrix. The circuit includes a first logic circuit (380-383)...
US-6,636,120 Decimated digital phase-locked loop for high-speed implementation
A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal...
US-6,636,116 Fully differential current feedback amplifier
A current feedback amplifier is disclosed for providing a differential output based on a single-ended or differential input signal, having first and second low...
US-6,636,084 Sample and hold circuit
A sample and hold circuit includes an operational amplifier and a plurality of switched capacitors, the switched capacitors introducing a closed loop gain of...
US-6,636,082 System and method for detecting a negative supply fault
A negative supply, low-voltage supply fault detection circuit is implemented without the need for a current mirror thereby providing for the elimination of...
US-6,636,076 Quad state logic design methods, circuits, and systems
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-6,636,067 Method of testing for micro latch-up
A reliable method of testing a CMOS-based integrated circuit device having a low-impedance path between I/O pin(s) and GND for potential micro-latch-up. The test...
US-6,636,063 Probe card with contact apparatus and method of manufacture
A probe card having reliable "micro probe" contacts which include a base and an angled probe tip fabricated as a single unit from a thin sheet of a conductive...
US-6,635,919 High Q-large tuning range micro-electro mechanical system (MEMS) varactor for broadband applications
A Micro Electro-Mechanical System (MEMS) varactor (100, 200) having a bottom electrode (116) formed over a substrate (112) and a dielectric material (130)...
US-6,635,916 On-chip capacitor
An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the ...
US-6,635,584 Versatile system for forming uniform wafer surfaces
A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an...
US-6,635,551 Deep trench isolation for reducing soft errors in integrated circuits
An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The...
US-6,635,550 Semiconductor on insulator device architecture and method of construction
An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14...
US-6,635,528 Method of planarizing a conductive plug situated under a ferroelectric capacitor
An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom...
US-6,635,498 Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a...
US-6,635,497 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other...
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of...
US-6,635,407 Two pass process for producing a fine pitch lead frame by etching
A method of fabricating a lead frame. The method includes providing an electrically conductive layer having a pair of opposing major surfaces. A pattern is...
US-6,635,229 Method for low perfluorocarbon compound emission
A method of reducing perfluorocarbon emissions wherein a plasma reactor or thermal chamber is provided and a gaseous single halogen-containing perfluorocarbon is...
US-6,634,368 Application of ozonated DI water to scrubbers for resist strip and particle removal processes
A method for resist strip and particle removal. Wafers (108) with a patterned resist formed thereon are placed on a wafer chuck (104) in a scrubber tool...
US-6,634,018 Optical proximity correction
An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process,...
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