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Use of a sacrificial layer to facilitate metallization for small features
A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108)...
Method for forming a mixed voltage circuit having complementary devices
A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a...
Methods for determining charging in semiconductor processing
Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric...
Method for controlling a semiconductor manufacturing process
A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process...
Method for power routing and distribution in an integrated circuit with
multiple interconnect layers
An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses...
METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA
STORAGE DEVICE, OR THE LIKE, USING A...
A method for writing data to a mass data storage device (10) includes applying a maximum transition run length code constraint to the data to be written,...
Multi-access, collision-based communications
A collision-based multi-access system is described which is capable of recovering collisions by means of jointly detecting the mutually interfering signals,...
Method and system for synchronizing serial data
A first embodiment of the present invention includes a decoder 320 and a detection circuit 330. The decoder 320 receives data at a packet rate. Each packet...
Element management system for a digital subscriber line access multiplexer
An access multiplexer (10) for a digital subscriber line (DSL) communications network, having element management system (EMS) capability, is disclosed. A host...
Semiconductor device array having dense memory cell array and hierarchical
bit line scheme
A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments...
Process and temperature resistant active damping circuit for inductive
An active damping circuit including an H-bridge circuit having an inductive load and a switching circuit, an impedance circuit responsive to a bias signal to...
System and method of maintaining an amplifier common-mode output voltage
A low-power solution for maintaining an amplifier common-mode output voltage, regardless of whether the amplifier is on or off, that does not degrade the...
VDS protection for high voltage swing applications
The invention provides apparatus, methods and systems for providing voltage protection at the drain-to-source path of an output transistor. The invention...
Frequency comparison circuit
The objective of the invention is to provide technology to give high-speed DVD RF signal reading. Frequency comparison circuit 1 of the present invention has edge...
Semiconductor device protective overcoat with enhanced adhesion to
An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging...
Method for fabricating an open can-type stacked capacitor on an uneven
An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150)...
Processes for chemical-mechanical polishing of a semiconductor wafer
A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at...
Sidewall process and method of implantation for improved CMOS with benefit
of low CGD, improved doping...
A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located...
Magnetic latch transport loader
A leadframe loader having a magnetic latch of predefined strength connecting a drive arm mechanism and a pusher system is the preferred embodiment of a transport...
Relocatable overland peripheral paging
Apparatus for flexibly locating the data page on which the peripheral registers are located. External hardware contentions are eliminated because the peripheral...
System and method of noise-dependent classification
A noise-dependent classifier for a speech recognition system includes a recognizer (15) that provides scores and score differences of two closest in-vocabulary...
Cascoded NPN electrostatic discharge protection circuit
The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar...
Inductive load driving circuit
The objective of the invention is to provide an inductive load driving circuit that can prevent occurrence of surge voltage. Output transistor 5 and auxiliary...
Battery pack with monitoring function utilizing association with a battery
A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being...
Substrate resistance ring
An embodiment of the invention is a doped region within the silicon substrate 20 of an integrated circuit where the silicon substrate 10 separates the doped...
Device and method of low voltage SCR protection for high voltage failsafe
A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS...
Etch-stopped SOI back-gate contact
The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without...
Ferroelectric capacitor plasma charging monitor
Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having...
Method of enhancing adhesion of a conductive barrier layer to an underlying
conductive plug and contact for...
An embodiment of the instant invention is a method of forming a conductive barrier layer on a dielectric layer, the method comprising the steps of: providing the...
Carbon doped epitaxial layer for high speed CB-CMOS
A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor...
Method and apparatus for fabricating self-aligned contacts in an integrated
An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond...
One step deposition process for the top electrode and hardmask in a
ferroelectric memory cell
One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride...
Testing method and apparatus assuring semiconductor device quality and
An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller...
Microprocessor with non-aligned scaled and unscaled addressing
A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is...
External direct memory access processor implementation that includes a
plurality of priority levels stored in...
An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one...
Method for rapid calibration of beverage dispensing machine
A rapid sensor calibration technique applied prior to each Sensor 9 measuring a beverage in which water (zero Brix), at same temperature as beverage, is drawn...
Wireless base station systems for packet communications
A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time...
Shared sense amplifier for ferro-electric memory cell
A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture....
Non-terminating pulse width modulation for displays
A method for using pulse-width modulation in displays. A series of PWM sequences is established. Each subsequent sequence clears the previous sequence before it,...
Stable low dropout, low impedance driver for linear regulators
A voltage regulator circuit that provides the current necessary to drive an output driver during transients and maintain low output impedance, while having a...
Dynamic threshold voltage 6T SRAM cell
An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a...
Method of growing surface aluminum nitride on aluminum films with low
An integrated circuit having an interconnect layer (104) that comprises a first barrier layer (106) and an aluminum-based layer (108) overlying the first barrier...
Using a carbon film as an etch hardmask for hard-to-etch materials
A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO.sub.2, RuO.sub.2, BST, PZT, SBT, FeNi, and FeNiCo and other used...
Method of providing polysilicon spacer for implantation
An improved method of implanting source and drain for CMOS devices is provided by a hard mask and dry etching to form polysilicon gates 20 percent longer than...
Method for producing wafer notches with rounded corners and a tool therefor
A semiconductor wafer for use in the fabrication of semiconductor devices which includes a circular wafer (13) of semiconductor material having a perimeter and a...
Single event upset tolerant microprocessor architecture
A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive...
Multiplier accumulator circuits
A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a...
Method and apparatus for glitchless signal generation
A digital system is provided with an interface circuit for interconnecting two modules in different clock domains. The interface circuit can selectively respond...
System and method for detecting interactions of people and vehicles
A video surveillance system that implements object detection and event recognition employing smart monitoring algorithms to analyze a video stream and recognize...
Portable computer with low voltage differential signaling adapter
A computer (10) uses a TTL-to-LVDS converter board (34) coupled to a graphics controller (32). The graphics controller (32) outputs video information using TTL...