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Patent # Description
US-6,570,516 Multi-output DAC and method using single DAC and multiple s/h circuits
A single-DAC, multiple sample/hold conversion circuit includes a digital-to-analog converter and a plurality of sample/hold circuits each including an output...
US-6,570,435 Integrated circuit with current limited charge pump and method
One aspect of the invention is an integrated circuit (613)comprising a current source (611) coupled to voltage source (610) and an output load (635). The...
US-6,570,415 Reduced voltage swing digital differential driver
A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a...
US-6,570,410 Feed-forward approach for timing skew in interleaved and double-sampled circuits
The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having...
US-6,570,398 Socket apparatus particularly adapted for LGA type semiconductor devices
A socket (10) has a cover (14) pivotably mounted to a base (12). The base is formed with a seat (12a) for mounting a semiconductor device on a contact mounting...
US-6,570,242 Bipolar transistor with high breakdown voltage collector
A transistor that includes a doped buried region 320 within a semiconductor body 300, 340. The doped buried region includes a portion having a first thickness...
US-6,570,181 Semiconductor metal interconnect reliability test structure
A semiconductor reliability test structure (10) is formed on a face of a semiconductor substrate. The test structure (10) includes a chain of a plurality of long...
US-6,569,741 Hydrogen anneal before gate oxidation
A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The...
US-6,569,734 Method for two-sided fabrication of a memory array
A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12,...
US-6,569,733 Gate device with raised channel and method
A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the...
US-RE38,126 Large die photolithography
An improved reticle (20) and method of using it to expose layers of wafers for large integrated circuits (10). The integrated circuit (10) is designed so that...
US-6,567,933 Emulation suspension mode with stop mode extension
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,567,910 Digital signal processing unit with emulation circuitry and debug interrupt enable register indicating...
An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating...
US-6,567,906 Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory
A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic...
US-6,567,895 Loop cache memory and cache controller for pipelined microprocessors
A microprocessor and method for operating this microprocessor are disclosed. The microprocessor contains multiple execution units that receive instructions from...
US-6,567,887 Buffering of partition tables, file system directory structures and individual file cluster chains in a mass...
A computer system for storing data includes a host computer having system RAM associated with the computer system, and a file directory peripheral bus connected...
US-6,567,559 Hybrid image compression with compression ratio control
A block based hybrid compression method with compression ratio control. The input page is classified as SOLID, TEXT, SATURATED TEXT or IMAGE type, and the...
US-6,567,489 Method and circuitry for acquiring a signal in a read channel
A method for acquiring a signal in a read channel (18), the read channel (18) having an equalizer (48), includes performing an automatic gain control sequence;...
US-6,567,346 Absolute time scale clock
An absolute time scale clock includes a radioactive isotope and a computer. The computer includes a processor that determines an indication of the current...
US-6,567,323 Memory circuit redundancy control
A memory having flexible column redundancy and flexible row redundancy plural column sticks, each column stick comprising a plurality of data lines. Positioned...
US-6,567,182 Scan conversion of polygons for printing file in a page description language
This invention cures many inefficiencies with known scan conversion methods. This invention employs a edge array rather than a set linked list from an array of...
US-6,567,153 Multiple image photolithography system and method
A multiple image photolithography system includes a radiation source (18) projecting electromagnetic radiation along a path. A reticle cartridge (26) is located...
US-6,567,134 Secondary color boost in sequential color systems
A method and system of increasing the intensity of secondary colors in sequential color display systems. The method utilizes light during a transition period...
US-6,567,021 Design-for-test circuit for successive approximation analog-to-digital converters
The present invention provides a method (30) of testing analog-to-digital converters (ADCs) (12) that shortens the test time required to measure INL and DNL by...
US-6,566,966 Fast lock/self-tuning VCO based PLL
A fast lock/self-tuning VCO based PLL integrated circuit (10) adapted for implementation in wireless communication systems requiring a high transfer data rate....
US-6,566,889 Line diagnostics for wireline modems
A modem with built-in transmission line diagnostic capability is presented. Said built-in line diagnostics are capable of determining said transmission line's...
US-6,566,266 Method of polishing a layer comprising copper using an oxide inhibitor slurry
A process for polishing a semiconductor body according to an embodiment of the present invention includes the steps of providing a semiconductor body, forming a...
US-6,566,211 Surface modified interconnects
An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to...
US-6,566,200 Flash memory array structure and method of forming
A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the...
US-6,564,946 Containment device for retaining semiconductor wafers
A containment device for retaining semiconductor wafers having a first housing member having a frame with inner and outer walls normal to the frame having a...
US-6,564,339 Emulation suspension mode handling multiple stops and starts
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,564,291 Multi-function peripheral storage device buffer system
The present invention provides a multi-function buffer system for use in a peripheral storage device system, as well as a peripheral storage device system having...
US-6,564,279 Method and apparatus facilitating insertion and removal of modules in a computer system
A computer system (10) includes a plurality of hot-plug sockets (30-33), each of which can be selectively uncoupled from a bus (59) during normal system...
US-6,564,115 Combined system, method and apparatus for wire bonding and testing
A combined system and method for computer-controlled bonding and testing of wire connections between integrated circuit chips and substrates, and for ...
US-6,564,046 Method of maintaining mobile terminal synchronization during idle communication periods
A method and structure of recovering a network time-base for radio data demodulation after an IDLE period of data communication gauges a local low frequency...
US-6,563,885 Decimated noise estimation and/or beamforming for wireless communications
A system and method facilitate estimating noise in a received signal. The received signal includes a plurality of data tones. Noise is estimated for a selected...
US-6,563,864 Residential power cutback for splitterless DSL operation
A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of...
US-6,563,655 Method and apparatus for failsafing and extending range for write precompensation
Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range...
US-6,563,618 Post connection dual IRDA port power management
Prior art attempts to reduce the power consumption demands of dual infrared transceiver laptop computer designs have.included enabling and disabling infrared...
US-6,563,448 Flexible sample rate converter for multimedia digital-to-analog conversion in a wireless telephone
A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog...
US-6,563,386 Self-starter for PLL synthesizers
Resuming the operation of a phase locked loop (PLL) that has entered a hang up status. The output of the PLL is examined to determine whether the output is stuck...
US-6,563,349 Multiplexor generating a glitch free output when selecting from multiple clock signals
A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the...
US-6,563,284 Single wire digital width modulation for fan control with tachometer feedback
The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor...
US-6,563,208 Semiconductor package with conductor impedance selected during assembly
A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary...
US-6,563,175 NMOS ESD protection device with thin silicide and methods for making same
An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor...
US-6,563,158 Method and apparatus for voltage stiffening in an integrated circuit
An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion...
US-6,563,155 Cross point type DRAM cell composed of a pillar having an active region
A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel...
US-6,562,724 Self-aligned stack formation
A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and...
US-6,561,868 System and method for controlling a polishing machine
A system for controlling a polishing machine during polishing of a workpiece, such as a semiconductor wafer, includes a carrier which has an interface surface...
US-6,560,734 IC with addressable test port
An integrated circuit (100) includes functional input and output signal leads (101,111), input and output circuits (102,112) connectes to the functional input...
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