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Patent # Description
US-6,616,967 Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process
An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In...
US-6,615,391 Current controlled multi-state parallel test for semiconductor device
A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and...
US-6,614,847 Content-based video compression
A video compression method and system including object-oriented compression plus error correction using decoder feedback.
US-6,614,703 Method and system for configuring integrated systems on a chip
A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method...
US-6,614,576 Surface micro-planarization for enhanced optical efficiency and pixel performance in SLM devices
A method for enhancing the optical performance of a reflective spatial light modulator by micro-planarizing surfaces within the SLM, such as the reflective...
US-6,614,466 Telescopic reconstruction of facial features from a speech pattern
To reduce the needed bandwidth of video communication system, a portion of the video image that differs from a preceding frame of the video image is predicted...
US-6,614,379 Precise differential voltage interpolation analog-to-digital converter having double interpolation using...
A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion...
US-6,614,375 Sigma-delta analog-to-digital converter having improved reference multiplexer
A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The...
US-6,614,310 Zero-overhead class G amplifier with threshold detection
The present invention provides an apparatus and method for operating driver amplifier (20) of a line driver circuit (10) from a lower set of power supply...
US-6,614,305 Method and circuit for trimming offset and temperature drift for operational amplifiers and voltage references
A trimming circuit and method of trimming is provided for offset and temperature drift trimming of an op amp or voltage reference device, having an input stage,...
US-6,614,297 Modulation scheme for filterless switching amplifiers with reduced EMI
A ternary modulation scheme for filterless switching amplifiers with reduced EMI reduces the common mode component of the signal by allowing only one state with...
US-6,614,276 Flip-flop design
A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29....
US-6,614,273 Ultra-fast voltage drive
An ultra-fast drive circuit (40) providing a rail-to-rail drive voltage at an output node (N.sub.1). A pair of bipolar output transistors (Q.sub.3, Q.sub.4) are...
US-6,614,262 Failsafe interface circuit with extended drain devices
Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad...
US-6,614,255 Digital method of measuring driver slew rates for reduced test time
A circuit combination (16,86) is presented for providing digital signals indicative of slew rates of drive signals (112,140) provided to H-bridge power drive...
US-6,614,247 Socket apparatus and method for removably mounting an electronic package
A socket (10) has a plurality of contacts (13) arranged in base (11). Each contact has one arm (13a) for contacting a solder ball of an electronic package (2). A...
US-6,613,700 Method for spin coating high viscosity materials on silicon wafers
A method for spin coating high viscosity materials. Two dispense steps are used. The first dispense step dispenses a small amount (102) of high viscosity...
US-6,613,698 Lower temperature method for forming high quality silicon-nitrogen dielectrics
A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick...
US-6,611,934 Boundary scan test cell circuit
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for...
US-6,611,857 Method and system for reducing power in a parallel-architecture multiplier
A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch...
US-6,611,796 Method and apparatus for combining memory blocks for in circuit emulation
An emulation device is provided that has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory within the emulation...
US-6,611,469 Asynchronous FIFO memory having built-in self test logic
An asynchronous First-In-First-Out memory integrated circuit is equipped with a Built-In Self Test logic structure which allows extensive full-frequency...
US-6,611,451 Memory array and wordline driver supply voltage differential in standby
An SRAM array 22, with improved leakage in standby, raises the wordline driver lower supply voltage Vss-WL when raising the array lower supply voltage Vss-array...
US-6,611,221 Multi-bit sigma-delta modulator employing dynamic element matching using adaptively randomized data-weighted...
A sigma-delta modulator disclosed herein provides a first order noise shaping of the errors associated with the multi bit DAC employing unit elements, without...
US-6,611,176 Method and apparatus for two zeros/two poles active compensation phase locked loops
A phase locked loop with two zeros/two poles active compensation. The two poles and two zeros provide increased stability with capability for narrow bandwidth...
US-6,611,163 Switched capacitor scheme for offset compensated comparators
An offset compensated comparator 70 has capacitors 80 and 81 coupled directly between the inputs of a preamplifier 78 and the outputs of a previous stage...
US-6,611,155 Internally and externally biased dual mode 1394 compliant driver
A dual mode output driver circuit within the architecture of a IEEE 1394-1995 IEEE 1394b compliant physical layer (PHY) circuit address the deficiencies of...
US-6,610,614 Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates
A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing...
US-6,609,163 Multi-channel serial port with programmable features
A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry...
US-6,608,905 Microphone bias current measurement circuit
A microphone bias current detection circuit includes: a microphone circuit 18; an amplifier 10 having a first output and a second output, the first output is...
US-6,608,865 Coding method for video signal based on the correlation between the edge direction and the distribution of the...
The objective of the invention is to make high-efficiency compressed coding for images. In coding of video signals in this application example, the edge is...
US-6,608,821 Method for collision avoidance in an asynchronous communication system
A method of avoiding collisions among a plurality of transmitters that communicate asynchronously in relation to each other with a single receiver. The...
US-6,608,792 Method and apparatus for storing data in an integrated circuit
A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the...
US-6,608,521 Pulse width modulation regulator control circuit having precise frequency and amplitude control
A control circuit (50) for a switch mode power converter having precise control of amplitude and frequency that does not exhibit overshoot error nor undershoot...
US-6,608,520 Regulator circuit
To provide a regulator circuit capable of preventing oscillation of output voltage when an overcurrent regulating function is activated voltage across resistor...
US-6,607,985 Gate stack and etch process
A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks...
US-6,606,687 Optimized hardware cleaning function for VIVT data cache
A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX...
US-6,606,686 Unified memory system architecture including cache and directly addressable static random access memory
A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is...
US-6,606,590 Emulation system with address comparison unit and data comparison unit ownership arbitration
In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation...
US-6,606,415 Feedback control for hybrid compression
A closed loop feedback system adaptively controls the compression ratio in a Raster Image Processor. The image content is analyzed in real time, and rasterized...
US-6,606,042 True background calibration of pipelined analog digital converters
Systems and methods are provided for performing a background calibration technique on one or more stages of a pipeline Analog-to-Digital Converter (ADC). The...
US-6,606,004 System and method for time dithering a digitally-controlled oscillator tuning input
A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register 1306 and a multiplexer 1308 responsive to a...
US-6,605,859 Buried Zener diode structure and method of manufacture
A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down...
US-6,605,540 Process for forming a dual damascene structure
The invention describes a method for forming a dual damascene structure. An etch stop layer (150) is formed on a dielectric layer (140). A second dielectric...
US-6,605,536 Treatment of low-k dielectric films to enable patterning of deep submicron features
Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H.sub.2 SO.sub.4) to improve patterning. Resist poisoning occurs due to an...
US-6,605,482 Process for monitoring the thickness of layers in a microelectronic device
A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material...
US-6,604,233 Method for optimizing the integrated circuit chip size for efficient manufacturing
The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and,...
US-6,604,154 Data processing device
Deter the lowering of the efficiency of data exchange in a data processing device that conducts data communications by using a serial bus conforming to the IEEF...
US-6,603,412 Interleaved coder and method
Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address...
US-6,603,366 Trimmable oscillator
The present invention relates to a trimmable oscillator circuit which comprises a comparator circuit operable to compare an output voltage of the oscillator...
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