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Patent # Description
US-6,781,887 Anti-fuse structure and method of writing and reading in integrated circuits
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an...
US-6,781,814 Capacitive pressure transducer
A capacitive fluid pressure transducer (10') has a sensing element (12) received in an electrically conductive cup-shaped shield member (24) which is crimped...
US-6,781,717 Threshold screening using range reduction
A screening method in a printer for approximating a gray scale tone with a more limited range image producer using a tree search. An input pixel packed data word...
US-6,781,623 Vertical compensation in a moving camera
A hand-held device comprising a housing (10) shaped and dimensioned to allow the device to be hand held, a display (12) secured to the housing for displaying...
US-6,781,536 Dual-stage digital-to-analog converter
A dual-stage DAC system is provided that includes a coarse resistor network having a first portion and a second portion that provide a plurality of segment...
US-6,781,463 Low voltage amplifier
An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier...
US-6,781,411 Flip flop with reduced leakage current
A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors...
US-6,781,204 Spreading the power dissipation in MOS transistors for improved ESD protection
An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid...
US-6,781,094 Analysis of MEMS mirror device using a laser for mirror removal
A method of analyzing a MEMS device having micromirrors. A laser is targeted on one or more mirror elements and used to remove only the mirror. Once the mirror...
US-6,780,756 Etch back of interconnect dielectrics
An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric...
US-6,780,749 Method of manufacturing a semiconductor chip comprising multiple bonding pads in staggard rows on edges
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is...
US-6,780,742 Undulated moat for reducing contact resistance
The present invention includes a method of forming a semiconductor device.
US-6,780,719 Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a...
US-6,780,673 Method of forming a semiconductor device package using a plate layer surrounding contact pads
A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive...
US-6,780,662 Selective deposition of emissive layer in electroluminescent displays
A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88)...
US-6,780,253 Gradient dragout system in a continuous plating line
An enhanced gradient dragout system conserves plating chemicals, including precious metals by providing a series of tanks with cascading rinse solutions having a...
US-6,780,250 System and method for integrated oxide removal and processing of a semiconductor wafer
An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single ...
US-6,779,133 IC with two state machines connected to serial scan path
A serial scan architecture (102-126) provides improved processor emulation capability.
US-6,779,085 TLB operation based on task-ID
A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation...
US-6,778,674 Hearing assist device with directional detection and sound modification
A hearing assist device (10) for a person (P). The device comprises a speaker device (SP1) for presenting sound to an ear canal of the person and circuitry for...
US-6,778,422 Ferroelectric memory
A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first...
US-6,778,216 Method and apparatus for digital camera real-time image correction in preview mode
A method for previewing an image in a camera prior to output. The method includes steps of gathering image data, storing the image data, calculating display...
US-6,778,155 Display operation with inserted block clears
An SLM PWM clocking method, called "jog clear," for generating short bit periods where block data clears (74) are inserted between block data loads (72, 76)...
US-6,778,113 Canceling feedback resister loading effect in a shunt-shunt feedback circuit
A shunt-shunt feedback current to voltage converter (60) including a compensating current (22) provided to the output of the amplifier (12) which mirrors the...
US-6,778,014 CMOS differential amplifier
A Complementary CMOS differential amplifier has automatic operating point adjustment (self-biasing) and the properties of a rail-to-rail amplifier. The CMOS...
US-6,778,005 High PSRR current source
The present invention improves on the topology of a conventional current source by interposing an RC circuit and additional MOS between the output of a buffer...
US-6,777,899 Circuit and method for removing increased power supply current spike that occurs during initial turn-on or...
A method and circuit (55) are presented for reducing a current spike (9) created after a commutation of a driving current of a polyphase motor (14). The motor...
US-6,777,300 Method to improve silicide formation on polysilicon
A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of...
US-6,776,688 Real-time polishing pad stiffness-control using magnetically controllable fluid
A method of CMP polishing of a semiconductor wafer is described that includes using a polishing pad on a platen/table with the polishing pad including a sub-pad...
US-6,775,801 Turbo decoder extrinsic normalization
This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and...
US-6,775,793 Data exchange system and method for processors
A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by...
US-6,775,778 Secure computing device having boot read only memory verification of program code
A secure computing system stores a program, preferably the real time operating system, that is encrypted with a private key. A boot ROM on the same integrated...
US-6,775,750 System protection map
A method and apparatus is provided for operating a digital system having several processors (102, 104) and peripheral devices (106, 116) connected to a shared...
US-6,775,732 Multiple transaction bus system
This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus...
US-6,775,649 Concealment of frame erasures for speech transmission and storage system and method
A decoder for packetized speech with differential quantization of line spectral frequencies and fixed-codebook gain conceals erased frames with interpolation of...
US-6,775,387 Three-step ramped reference to reduce popping noises on audio circuit
Provided is a method (500) and audio circuit (100) for reducing popping noise in a load (140, 145) connected to the audio circuit, especially during audio...
US-6,775,335 Method and apparatus for equalization and tracking of coded digital communications signals
A symbol detector provides a delay-less estimate of a transmitted symbol. The symbol detector includes a symbol input for receiving a sequence of input symbols,...
US-6,775,260 Space time transmit diversity for TDD/WCDMA systems
A circuit is designed with a matched filter circuit including a plurality of fingers (700, 702, 704) coupled to receive a data symbol. Each finger corresponds to...
US-6,775,174 Memory architecture for micromirror cell
A one transistor one capacitor micromirror with DRAM memory cell built around a large polysilicon-to-substrate capacitor which is not susceptible to...
US-6,775,118 Supply voltage reference circuit
A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output...
US-6,775,078 Fast magneto-resistive head open and short detection for both voltage and current bias preamplifiers
A circuit and method are presented for detecting a fault in a magneto-resistive head (18). The circuit includes a bias circuit (50) to produce a bias voltage...
US-6,775,049 Optical digital signal processing system and method
A method for optical digital signal processing, comprises configuring a plurality of binary mirrors to allow a subset of the binary mirrors to represent a range...
US-6,774,916 Contour mitigation using parallel blue noise dithering system
A method and system for displaying fractional bit data in order to increase the bit depth of a PWM display without requiring the use of an excessive number of...
US-6,774,617 Peak detector for detecting a peak signal
A peak detector for detecting a peak signal includes an input circuit to input an input signal, a track and hold circuit to hold the input signal and to output...
US-6,774,496 Semiconductor package with a thermoset bond
A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer...
US-6,774,489 Dielectric layer liner for an integrated circuit structure
An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically...
US-6,774,485 Apparatus for and method of packaging semiconductor devices
A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one...
US-6,774,457 Rectangular contact used as a low voltage fuse element
A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse...
US-6,774,455 Semiconductor device with a collector contact in a depressed well-region
A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a...
US-6,774,031 Method of forming dual-damascene structure
A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second...
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