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Patent # Description
US-6,586,267 Transient fuse for charge-induced damage detection
A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the...
US-6,584,588 System signalling schemes for processor & memory module
A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and...
US-6,584,536 Bus transaction accelerator for multi-clock systems
A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different...
US-6,584,514 Apparatus and method for address modification in a direct memory access controller
In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory...
US-6,584,369 Method and system for dispatching semiconductor lots to manufacturing equipment for fabrication
A method for dispatching available lots to unallocated machines is provided that includes receiving metrics data (26) providing performance measurements for a...
US-6,583,946 Method of providing read bias during servo block write
The manufacturer of hard disk drives (HDD) simultaneously activates all write heads to format the magnetoresistive disks during an operation known in the...
US-6,583,921 Micromechanical device and method for non-contacting edge-coupled operation
A new non-contacting, edge-coupled micromechanical device and method, requiring no contact between the mirror or underlying yoke and landing pads on the...
US-6,583,744 Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC
A current correction circuit 500 eliminates beta mismatches between a thermometer encoded segment 102 and a R-2R ladder segment 106 of a current steering...
US-6,583,639 Reduced cost, high speed circuit test arrangement
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate...
US-6,583,515 Ball grid array package for enhanced stress tolerance
The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like...
US-6,583,500 Thin tin preplated semiconductor leadframes
A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of...
US-6,583,483 Semiconductor device and its manufacturing method
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is...
US-6,583,427 Extended life source arc chamber liners
A liner (102) for an arc chamber (100) of an ion implanter. The arc chamber (100) comprises a liner (102) on the inner surface (104) of the arc chamber (100)...
US-6,583,058 Solid hermetic via and bump fabrication
A method of forming an electrically conductive via with bumps on both sides of a substrate wherein there is provided a substrate having a pair of opposing...
US-6,583,053 Use of a sacrificial layer to facilitate metallization for small features
A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108)...
US-6,583,013 Method for forming a mixed voltage circuit having complementary devices
A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a...
US-6,582,977 Methods for determining charging in semiconductor processing
Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric...
US-6,582,973 Method for controlling a semiconductor manufacturing process
A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process...
US-6,581,201 Method for power routing and distribution in an integrated circuit with multiple interconnect layers
An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses...
US-6,581,184 METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA STORAGE DEVICE, OR THE LIKE, USING A...
A method for writing data to a mass data storage device (10) includes applying a maximum transition run length code constraint to the data to be written,...
US-6,581,177 Multi-access, collision-based communications
A collision-based multi-access system is described which is capable of recovering collisions by means of jointly detecting the mutually interfering signals,...
US-6,581,114 Method and system for synchronizing serial data
A first embodiment of the present invention includes a decoder 320 and a detection circuit 330. The decoder 320 receives data at a packet rate. Each packet...
US-6,580,727 Element management system for a digital subscriber line access multiplexer
An access multiplexer (10) for a digital subscriber line (DSL) communications network, having element management system (EMS) capability, is disclosed. A host...
US-6,580,629 Semiconductor device array having dense memory cell array and hierarchical bit line scheme
A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments...
US-6,580,575 Process and temperature resistant active damping circuit for inductive write drivers
An active damping circuit including an H-bridge circuit having an inductive load and a switching circuit, an impedance circuit responsive to a bias signal to...
US-6,580,315 System and method of maintaining an amplifier common-mode output voltage
A low-power solution for maintaining an amplifier common-mode output voltage, regardless of whether the amplifier is on or off, that does not degrade the...
US-6,580,308 VDS protection for high voltage swing applications
The invention provides apparatus, methods and systems for providing voltage protection at the drain-to-source path of an output transistor. The invention...
US-6,580,297 Frequency comparison circuit
The objective of the invention is to provide technology to give high-speed DVD RF signal reading. Frequency comparison circuit 1 of the present invention has edge...
US-6,580,170 Semiconductor device protective overcoat with enhanced adhesion to polymeric materials
An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging...
US-6,580,112 Method for fabricating an open can-type stacked capacitor on an uneven surface
An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150)...
US-6,579,798 Processes for chemical-mechanical polishing of a semiconductor wafer
A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at...
US-6,579,770 Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping...
A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located...
US-6,578,703 Magnetic latch transport loader
A leadframe loader having a magnetic latch of predefined strength connecting a drive arm mechanism and a pusher system is the preferred embodiment of a transport...
US-6,578,123 Relocatable overland peripheral paging
Apparatus for flexibly locating the data page on which the peripheral registers are located. External hardware contentions are eliminated because the peripheral...
US-6,577,997 System and method of noise-dependent classification
A noise-dependent classifier for a speech recognition system includes a recognizer (15) that provides scores and score differences of two closest in-vocabulary...
US-6,577,481 Cascoded NPN electrostatic discharge protection circuit
The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar...
US-6,577,173 Inductive load driving circuit
The objective of the invention is to provide an inductive load driving circuit that can prevent occurrence of surge voltage. Output transistor 5 and auxiliary...
US-6,577,135 Battery pack with monitoring function utilizing association with a battery charging system
A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being...
US-6,576,961 Substrate resistance ring
An embodiment of the invention is a doped region within the silicon substrate 20 of an integrated circuit where the silicon substrate 10 separates the doped...
US-6,576,959 Device and method of low voltage SCR protection for high voltage failsafe ESD applications
A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS...
US-6,576,957 Etch-stopped SOI back-gate contact
The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without...
US-6,576,922 Ferroelectric capacitor plasma charging monitor
Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having...
US-6,576,546 Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for...
An embodiment of the instant invention is a method of forming a conductive barrier layer on a dielectric layer, the method comprising the steps of: providing the...
US-6,576,535 Carbon doped epitaxial layer for high speed CB-CMOS
A method for fabricating a high speed complementary bipolar/CMOS device is disclosed which enables the forming of a silicon epitaxial layer in a PNP transistor...
US-6,576,519 Method and apparatus for fabricating self-aligned contacts in an integrated circuit
An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond...
US-6,576,482 One step deposition process for the top electrode and hardmask in a ferroelectric memory cell
One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride...
US-6,574,760 Testing method and apparatus assuring semiconductor device quality and reliability
An automatic test apparatus for assuring quality and reliability of semiconductor integrated circuit devices comprising a computerized tester controller...
US-6,574,724 Microprocessor with non-aligned scaled and unscaled addressing
A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is...
US-6,574,683 External direct memory access processor implementation that includes a plurality of priority levels stored in...
An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one...
US-6,574,575 Method for rapid calibration of beverage dispensing machine
A rapid sensor calibration technique applied prior to each Sensor 9 measuring a beverage in which water (zero Brix), at same temperature as beverage, is drawn...
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