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Patent # Description
US-6,567,346 Absolute time scale clock
An absolute time scale clock includes a radioactive isotope and a computer. The computer includes a processor that determines an indication of the current...
US-6,567,323 Memory circuit redundancy control
A memory having flexible column redundancy and flexible row redundancy plural column sticks, each column stick comprising a plurality of data lines. Positioned...
US-6,567,182 Scan conversion of polygons for printing file in a page description language
This invention cures many inefficiencies with known scan conversion methods. This invention employs a edge array rather than a set linked list from an array of...
US-6,567,153 Multiple image photolithography system and method
A multiple image photolithography system includes a radiation source (18) projecting electromagnetic radiation along a path. A reticle cartridge (26) is located...
US-6,567,134 Secondary color boost in sequential color systems
A method and system of increasing the intensity of secondary colors in sequential color display systems. The method utilizes light during a transition period...
US-6,567,021 Design-for-test circuit for successive approximation analog-to-digital converters
The present invention provides a method (30) of testing analog-to-digital converters (ADCs) (12) that shortens the test time required to measure INL and DNL by...
US-6,566,966 Fast lock/self-tuning VCO based PLL
A fast lock/self-tuning VCO based PLL integrated circuit (10) adapted for implementation in wireless communication systems requiring a high transfer data rate....
US-6,566,889 Line diagnostics for wireline modems
A modem with built-in transmission line diagnostic capability is presented. Said built-in line diagnostics are capable of determining said transmission line's...
US-6,566,266 Method of polishing a layer comprising copper using an oxide inhibitor slurry
A process for polishing a semiconductor body according to an embodiment of the present invention includes the steps of providing a semiconductor body, forming a...
US-6,566,211 Surface modified interconnects
An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to...
US-6,566,200 Flash memory array structure and method of forming
A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the...
US-6,564,946 Containment device for retaining semiconductor wafers
A containment device for retaining semiconductor wafers having a first housing member having a frame with inner and outer walls normal to the frame having a...
US-6,564,339 Emulation suspension mode handling multiple stops and starts
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,564,291 Multi-function peripheral storage device buffer system
The present invention provides a multi-function buffer system for use in a peripheral storage device system, as well as a peripheral storage device system having...
US-6,564,279 Method and apparatus facilitating insertion and removal of modules in a computer system
A computer system (10) includes a plurality of hot-plug sockets (30-33), each of which can be selectively uncoupled from a bus (59) during normal system...
US-6,564,115 Combined system, method and apparatus for wire bonding and testing
A combined system and method for computer-controlled bonding and testing of wire connections between integrated circuit chips and substrates, and for ...
US-6,564,046 Method of maintaining mobile terminal synchronization during idle communication periods
A method and structure of recovering a network time-base for radio data demodulation after an IDLE period of data communication gauges a local low frequency...
US-6,563,885 Decimated noise estimation and/or beamforming for wireless communications
A system and method facilitate estimating noise in a received signal. The received signal includes a plurality of data tones. Noise is estimated for a selected...
US-6,563,864 Residential power cutback for splitterless DSL operation
A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of...
US-6,563,655 Method and apparatus for failsafing and extending range for write precompensation
Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range...
US-6,563,618 Post connection dual IRDA port power management
Prior art attempts to reduce the power consumption demands of dual infrared transceiver laptop computer designs have.included enabling and disabling infrared...
US-6,563,448 Flexible sample rate converter for multimedia digital-to-analog conversion in a wireless telephone
A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog...
US-6,563,386 Self-starter for PLL synthesizers
Resuming the operation of a phase locked loop (PLL) that has entered a hang up status. The output of the PLL is examined to determine whether the output is stuck...
US-6,563,349 Multiplexor generating a glitch free output when selecting from multiple clock signals
A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the...
US-6,563,284 Single wire digital width modulation for fan control with tachometer feedback
The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor...
US-6,563,208 Semiconductor package with conductor impedance selected during assembly
A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary...
US-6,563,175 NMOS ESD protection device with thin silicide and methods for making same
An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor...
US-6,563,158 Method and apparatus for voltage stiffening in an integrated circuit
An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion...
US-6,563,155 Cross point type DRAM cell composed of a pillar having an active region
A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel...
US-6,562,724 Self-aligned stack formation
A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and...
US-6,561,868 System and method for controlling a polishing machine
A system for controlling a polishing machine during polishing of a workpiece, such as a semiconductor wafer, includes a carrier which has an interface surface...
US-6,560,734 IC with addressable test port
An integrated circuit (100) includes functional input and output signal leads (101,111), input and output circuits (102,112) connectes to the functional input...
US-6,560,722 Developing and deploying real-time high-performance applications with DSPs
To address the need for enhanced real-time analysis, Texas Instruments Inc. has developed a standard embedded infrastructure for its DSPs that provides unique...
US-6,560,294 Phase estimation in carrier recovery of phase-modulated signals such as QAM signals
A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated...
US-6,560,288 Method and system for variable length decoding
Variable length codes in a compressed data stream are identified by determining a leading position of a specified value in the compressed data stream. A length...
US-6,560,127 Power conversion circuit having improved zero voltage switching
A highly efficient and simple power conversion circuit (300) having zero voltage switching (ZVS) includes a novel switch timing technique, such that the need for...
US-6,559,714 Signal filter with adjustable analog impedance selected by digital control
A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C...
US-6,559,702 Bias generator and method for improving output skew voltage
A method as well as a bias generator and associated output circuit architecture (300) that protects output skew voltage capabilities for the associated output...
US-6,559,523 Device for attaching a semiconductor chip to a chip carrier
In a device for attaching a semiconductor chip (10) to a chip carrier (12), thereby producing an electrically conducting connection between contact areas (22,...
US-6,559,050 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices
A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride...
US-6,559,019 Breakdown drain extended NMOS
An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank...
US-6,558,049 System for processing video in computing devices that multiplexes multiple video streams into a single video...
This is a system and method of processing multiple video streams for a computing device. The system may comprise: a central processing device; a communications...
US-6,557,116 Emulation suspension mode with frame controlled resource access
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,557,097 Linear vector computation
A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The...
US-6,556,575 Broadcast traffic reduction in a communications network
The present invention includes a method and system for routing broadcast packets in a network (250) using a switching device (200) which is operable to...
US-6,556,408 Compensation circuit for leakage through electrostatic discharge protection devices
A mixed-signal integrated circuit (12) having compensation for leakage through an ESD cell (16) at an external terminal of a reference voltage is disclosed. A...
US-6,556,088 Phase-locked loop having a stable damping factor
A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second...
US-6,556,087 Fractional frequency division frequency synthesizer having rounded phase control value
In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency...
US-6,556,081 Single-ended, ultra low voltage class AB power amplifier architecture having a common-mode feedback quiescent...
A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control...
US-6,556,077 Instrumentation amplifier with improved AC common mode rejection performance
A method and apparatus for improving the AC common mode rejection performance of monolithic two op-amp instrumentation amplifiers is disclosed. A new approach to...
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