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Patent # Description
US-6,549,512 MDSL DMT architecture
A DMT device having an analog front end for receiving an analog signal, a converter for converting the analog signal to a digital signal, a FFT for converting...
US-6,549,357 Selectable input pole compensation for a disk drive read head
A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in...
US-6,549,353 Overshoot control for a hard disk drive write head
An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and...
US-6,549,338 Bandpass filter to reduce thermal impact of dichroic light shift
A color splitting prism assembly (100) comprised of three prisms. Each a dichroic filter at an interface (112) between a first and second of the three prisms...
US-6,549,155 Signal conversion using coarse and fine digital to analog converters
Signal conversion apparatus and method with coarse and fine digital to analog converters. The output of the coarse DAC has a high gain to support wide voltage...
US-6,549,138 Method and apparatus for providing detection of excessive negative offset of a sensor
Detection of excessive negative offset of a condition responsive sensor such as a pressure responsive full Wheatstone bridge element (10) and circuitry...
US-6,549,049 Dynamic voltage reference circuit
A differential pair input receiver (30) having variable reference voltages that may be customized by the designer so as to increase and decrease noise margins of...
US-6,548,997 Mechanism for measurement of time duration between asynchronous events
A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting...
US-6,548,973 Method and apparatus for braking a polyphase DC motor
A circuit (10) for braking a polyphase dc motor (12) includes a circuit (38) for producing an output signal indicating that the motor has slowed at least to an...
US-6,548,942 Encapsulated packaging for thin-film resonators and thin-film resonator-based filters having a piezoelectric...
An acoustic reflector (48) is applied over a thin-film piezoelectric resonator (41, 61) which is supported on a semiconductor or semiconductor-compatible...
US-6,548,924 Protective device for a hermetically sealed type compressor and a hermetically sealed compressor listing same
A protective device (3) for a hermetic type electromotively driven compressor (1a) includes a protector assembly (30) having a housing (32) with an electric...
US-6,548,874 Higher voltage transistors for sub micron CMOS processes
An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS...
US-6,548,841 Nanomechanical switches and circuits
A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its...
US-6,548,400 Method of fabricating interlevel connectors using only one photomask step
A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one...
US-6,548,366 Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a...
US-6,548,362 Method of forming MOSFET with buried contact and air-gap gate structure
A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad...
US-6,548,359 Asymmetrical devices for short gate length performance with disposable sidewall
An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V.sub.T net dopant adjacent...
US-6,548,343 Method of fabricating a ferroelectric memory cell
An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps...
US-6,547,580 Socket apparatus particularly adapted for land grid array type semiconductor devices
A socket (10) has a cover (14) pivotably mounted to a base (12). The base is formed with a seat (12a) for mounting a semiconductor device on a contact mounting...
US-6,546,518 Detector error suppression circuit and method
Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to...
US-6,546,510 Burn-in mode detect circuit for semiconductor device
A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under...
US-6,546,505 Processor condition sensing circuits, systems and methods
A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor...
US-6,546,477 Memory management in embedded systems with dynamic object instantiation
A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is...
US-6,546,407 Reduced computation digital filter
A method for providing a multi-stage filter on an input stream of digital data. In the method, the input stream of digital data is operated on with a first...
US-6,545,903 Self-aligned resistive plugs for forming memory cell with phase change material
Memory devices are disclosed for storage and retrieval of information, wherein resistive plugs are provided above and below a phase change material to form a...
US-6,545,814 Optical architectures for combining multiple lamps in light valve projectors
An integrating rod (100) for combining light beams from two or more sources. A first light beam (104) enters the integrating rod 100 through a first entrance...
US-6,545,740 Method and system for reducing motion artifacts
A motion artifact reduction system (10) includes a series of cinematic feature image frames (IF.sub.m, IF.sub.m+1)captured at an incoming frame rate. The motion...
US-6,545,623 High speed analog-domain shuffler for analog to digital converter
A method for use in a system including an analog-to-digital converter subsystem (ADC) and a digital-to-analog converter subsystem (DAC), wherein the ADC samples...
US-6,545,549 Remotely controllable phase locked loop clock circuit
This invention is a remotely controllable clock circuit embodied in a single integrated circuit device. The clock circuit includes at least one externally...
US-6,545,547 Method for tuning a VCO using a phase lock loop
A very fast lock integer N PLL with hybrid digital coarse VCO tuning and VCO temperature drift compensation provides for a fully digital tuning scheme without...
US-6,545,538 Rail-to-rail class AB output stage for operational amplifier with wide supply range
A rail-to-rail class AB output stage includes a P-channel pull-up transistor (4) having a source coupled to a first supply rail voltage (V.sup.+), a gate coupled...
US-6,545,533 Class D audio speaker amplifier circuit with pseudo noise modulation
The present invention relates to a Class D amplifier and method dynamically modulate the transition zone of a square wave as a function of the input signal. An...
US-6,545,511 Adjustable temperature-compensated threshold circuit with trip-points exceeding the given supplies
The temperature compensated threshold circuit includes: a positive trip point circuit 60 for providing a positive trip point when an input voltage PSM is higher...
US-6,545,507 Fast locking CDR (clock and data recovery circuit) with high jitter tolerance and elimination of effects caused...
A system 400 and method 1200 is disclosed for a fast locking (e.g., within 1.5 sync bit times or the first data transition) clock and data recovery (CDR) system...
US-6,545,344 Semiconductor leadframes plated with lead-free solder and minimum palladium
A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of...
US-6,545,342 Pre-finished leadframe for semiconductor devices and method of fabrication
A leadframe for use with integrated circuit chips comprising a base metal, usually copper or a copper alloy, having a modified surface adapted to provide...
US-6,544,906 Annealing of high-k dielectric materials
A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in...
US-6,544,886 Process for isolating an exposed conducting surface
A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not...
US-6,544,875 Chemical vapor deposition of silicate high dielectric constant materials
A method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a conductive structure over the...
US-6,544,816 Method of encapsulating thin semiconductor chip-scale packages
An apparatus for the fabrication of a semiconductor device comprising: a mold having top and bottom halves, each with cavities for holding semiconductor chips...
US-6,543,048 Debugger with real-time data exchange
A collection of program instructions capable of executing on a host processor suitable for reading from a memory location of a target processor and suitable for...
US-6,542,621 Method of dealing with occlusion when tracking multiple objects and people in video sequences
This invention employs probabilistic templates, or p-templates, which probabilistically encode the rough position and extent of the tracked object's image. The...
US-6,542,547 Efficient heuristic based motion estimation method for video compression
A heuristic based motion estimation system and method for video compression may include: defining the target block 70; defining a simplified signature block 72;...
US-6,542,282 Post metal etch clean process using soft mask
A method of patterning a metal layer that cleans the residue from a metal etch process without removing a photoresist etch mask. The method is particularly...
US-6,542,221 Integrated circuit system with automated best focus determination based on change in alignment due to...
A method (40) of determining a best focus for an integrated circuit stepper (10). The method repeats various steps for a plurality of different focus levels. The...
US-6,542,032 Extremely linear, high speed, class AB rail to rail bipolar amplifier output stage with high output drive
The amplifier output stage circuit includes: a translinear loop 30 having first and second input nodes Vin+ and Vin-; a first transistor Q7 coupled between a...
US-6,542,017 Feed-forward approach for timing skew in interleaved and double-sampled circuits
The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having...
US-6,542,015 Duty cycle correction circuit and apparatus and method employing same
A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected...
US-6,542,009 Signal hold circuit
A peak hold circuit that can operate to follow changes in peak value even if the changes are abrupt. The peak hold circuit (1) of the present invention has...
US-6,541,952 On-line cancellation of sampling mismatch in interleaved sample-and-hold circuits
The present invention relates to a high speed sample and hold circuit having a plurality of sample and hold subcircuits coupled in parallel between an input and...
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