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Patent # Description
US-6,591,390 CRC-based adaptive halting turbo decoder and method of use
A CRC-based adaptive halting turbo decoder applies a CRC code to identify internally generated information sequences. The information sequences are encoded with...
US-6,591,230 Coprocessor for synthesizing signals based upon quadratic polynomial sinusoids
A coprocessor (15) for synthesizing a signal from the sum of sinusoids preferably includes an electronic system (20) having a host processor (12) that forwards...
US-6,591,205 Pseudo arbitrary waveform generator
A method of waveform generation using a VLSI digital tester unit without an arbitrary waveform generator. A software application produces a series of vectors to...
US-6,591,022 Illumination system for scrolling color recycling
Distortion optics are used to efficiently couple a spiral color wheel and an orthogonal modulator. Light 602 from a light source enters an aperture in a...
US-6,590,884 Method and apparatus providing spatial diversity within an indoor network
A method and architecture that provides network level spatial diversity using multiple indoor access points (70) has a transceiver coupled to each wireless...
US-6,590,843 DVD radial runout cancellation with self-calibration
A self-calibrating radial runout cancellation method for DVD optical disc media. The radial runout of an optical disc is first measured, during closed-loop...
US-6,590,799 On-chip charge distribution measurement circuit
A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A...
US-6,590,798 Apparatus and methods for imprint reduction for ferroelectric memory cell
Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory...
US-6,590,549 Analog pulse width modulation of video data
A micromirror capable of analog pulse width modulation, and method thereof A capacitor (406) in each micromirror element stores a charge representative of one...
US-6,590,513 Data acquisition system using predictive conversion
A data acquisition system uses an analog-to-digital converter (ADC) that includes a prediction feedback element. Using the computing power of a digital signal...
US-6,590,458 Clock generator circuit with a PLL having an output frequency cycled in a range to reduce unwanted radiation
A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL...
US-6,590,448 Operational amplifier topology and method
A technique is disclosed which facilitates the layout of op amp cells, for example, two-stage op amp cells or three-stage op amp cells, to provide larger...
US-6,590,436 System and method of translating wide common mode voltage ranges into narrow common mode voltage ranges
A system and method is provided for translating a wide common mode voltage range into a narrow common mode voltage range. The system and method extend the common...
US-6,590,431 Maintaining substantially constant trans-conductance without substantially changing power consumption
The current passing in a main trans-conductor circuit is compared in analog domain with a reference current. If the passing current exceeds the reference...
US-6,590,225 Die testing using top surface test pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...
US-6,589,865 Low pressure, low temperature, semiconductor gap filling process
A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures...
US-6,589,800 Method of estimation of wafer-to-wafer thickness
A method for extracting wafer-to-wafer thickness variation from interferometry signals off patterned (product) wafer polish during non-endpointed CMP. The method...
US-6,587,689 Multi-sensor assisted cellular handoff technique
A system and method for assisting in handoff in a cellular communication system. The system includes a base station having a data base of patterns of known...
US-6,587,529 Phase detector architecture for phase error estimating and zero phase restarting
A system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks...
US-6,587,378 Apparatus and method for refreshing a flash memory unit
In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that...
US-6,587,367 Dummy cell structure for 1T1C FeRAM cell array
A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device...
US-6,587,296 Capacitor bias recovery methodology
A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier...
US-6,587,159 Projector for digital cinema
A digital cinema projection system (200) for projecting images onto a display screen. The projection system (200) comprises a lamp console (102) and a projector...
US-6,587,062 Flexible interface circuit and method for delta sigma A/D converters
A multi-mode interface circuit for coupling a delta sigma modulator (24) to a processor includes a decoder 20 for decoding mode selection inputs to produce a...
US-6,586,985 Methods and apparatus for trimming packaged electrical devices
An electrical device is disclosed, comprising electrical components forming an electrical circuit, with a trim circuit comprising two or more trim cells...
US-6,586,839 Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers
A conductive via pattern (110) between the uppermost metal interconnect layer (M.sub.n) and next underlying metal interconnect layer (M.sub.n-1) in the bond pad...
US-6,586,676 Plastic chip-scale package having integrated passive components
A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic...
US-6,586,334 Reducing copper line resistivity by smoothing trench and via sidewalls
A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106)....
US-6,586,315 Whole wafer MEMS release process
A process for manufacturing a wafer having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. The devices on the wafer...
US-6,586,267 Transient fuse for charge-induced damage detection
A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the...
US-6,584,588 System signalling schemes for processor & memory module
A computer system includes a main processing unit (12) coupled to a DSP/memory module (40). The DSP/memory module (40) includes semiconductor memory (42) and...
US-6,584,536 Bus transaction accelerator for multi-clock systems
A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different...
US-6,584,514 Apparatus and method for address modification in a direct memory access controller
In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory...
US-6,584,369 Method and system for dispatching semiconductor lots to manufacturing equipment for fabrication
A method for dispatching available lots to unallocated machines is provided that includes receiving metrics data (26) providing performance measurements for a...
US-6,583,946 Method of providing read bias during servo block write
The manufacturer of hard disk drives (HDD) simultaneously activates all write heads to format the magnetoresistive disks during an operation known in the...
US-6,583,921 Micromechanical device and method for non-contacting edge-coupled operation
A new non-contacting, edge-coupled micromechanical device and method, requiring no contact between the mirror or underlying yoke and landing pads on the...
US-6,583,744 Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC
A current correction circuit 500 eliminates beta mismatches between a thermometer encoded segment 102 and a R-2R ladder segment 106 of a current steering...
US-6,583,639 Reduced cost, high speed circuit test arrangement
An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate...
US-6,583,515 Ball grid array package for enhanced stress tolerance
The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like...
US-6,583,500 Thin tin preplated semiconductor leadframes
A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal and a plated layer of...
US-6,583,483 Semiconductor device and its manufacturing method
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is...
US-6,583,427 Extended life source arc chamber liners
A liner (102) for an arc chamber (100) of an ion implanter. The arc chamber (100) comprises a liner (102) on the inner surface (104) of the arc chamber (100)...
US-6,583,058 Solid hermetic via and bump fabrication
A method of forming an electrically conductive via with bumps on both sides of a substrate wherein there is provided a substrate having a pair of opposing...
US-6,583,053 Use of a sacrificial layer to facilitate metallization for small features
A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108)...
US-6,583,013 Method for forming a mixed voltage circuit having complementary devices
A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a...
US-6,582,977 Methods for determining charging in semiconductor processing
Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric...
US-6,582,973 Method for controlling a semiconductor manufacturing process
A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process...
US-6,581,201 Method for power routing and distribution in an integrated circuit with multiple interconnect layers
An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses...
US-6,581,184 METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA STORAGE DEVICE, OR THE LIKE, USING A...
A method for writing data to a mass data storage device (10) includes applying a maximum transition run length code constraint to the data to be written,...
US-6,581,177 Multi-access, collision-based communications
A collision-based multi-access system is described which is capable of recovering collisions by means of jointly detecting the mutually interfering signals,...
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