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Patent # Description
US-6,563,864 Residential power cutback for splitterless DSL operation
A digital subscriber line modem (30) capable of operating with multiple transmission line profiles depending on the current transmission line characteristics of...
US-6,563,655 Method and apparatus for failsafing and extending range for write precompensation
Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range...
US-6,563,618 Post connection dual IRDA port power management
Prior art attempts to reduce the power consumption demands of dual infrared transceiver laptop computer designs have.included enabling and disabling infrared...
US-6,563,448 Flexible sample rate converter for multimedia digital-to-analog conversion in a wireless telephone
A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog...
US-6,563,386 Self-starter for PLL synthesizers
Resuming the operation of a phase locked loop (PLL) that has entered a hang up status. The output of the PLL is examined to determine whether the output is stuck...
US-6,563,349 Multiplexor generating a glitch free output when selecting from multiple clock signals
A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the...
US-6,563,284 Single wire digital width modulation for fan control with tachometer feedback
The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor...
US-6,563,208 Semiconductor package with conductor impedance selected during assembly
A semiconductor package having a plurality of conductors arrayed in two (or more) parallel planes, and an available ground conductor. Conductors in the auxiliary...
US-6,563,175 NMOS ESD protection device with thin silicide and methods for making same
An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor...
US-6,563,158 Method and apparatus for voltage stiffening in an integrated circuit
An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion...
US-6,563,155 Cross point type DRAM cell composed of a pillar having an active region
A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel...
US-6,562,724 Self-aligned stack formation
A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and...
US-6,561,868 System and method for controlling a polishing machine
A system for controlling a polishing machine during polishing of a workpiece, such as a semiconductor wafer, includes a carrier which has an interface surface...
US-6,560,734 IC with addressable test port
An integrated circuit (100) includes functional input and output signal leads (101,111), input and output circuits (102,112) connectes to the functional input...
US-6,560,722 Developing and deploying real-time high-performance applications with DSPs
To address the need for enhanced real-time analysis, Texas Instruments Inc. has developed a standard embedded infrastructure for its DSPs that provides unique...
US-6,560,294 Phase estimation in carrier recovery of phase-modulated signals such as QAM signals
A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated...
US-6,560,288 Method and system for variable length decoding
Variable length codes in a compressed data stream are identified by determining a leading position of a specified value in the compressed data stream. A length...
US-6,560,127 Power conversion circuit having improved zero voltage switching
A highly efficient and simple power conversion circuit (300) having zero voltage switching (ZVS) includes a novel switch timing technique, such that the need for...
US-6,559,714 Signal filter with adjustable analog impedance selected by digital control
A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C...
US-6,559,702 Bias generator and method for improving output skew voltage
A method as well as a bias generator and associated output circuit architecture (300) that protects output skew voltage capabilities for the associated output...
US-6,559,523 Device for attaching a semiconductor chip to a chip carrier
In a device for attaching a semiconductor chip (10) to a chip carrier (12), thereby producing an electrically conducting connection between contact areas (22,...
US-6,559,050 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices
A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride...
US-6,559,019 Breakdown drain extended NMOS
An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank...
US-6,558,049 System for processing video in computing devices that multiplexes multiple video streams into a single video...
This is a system and method of processing multiple video streams for a computing device. The system may comprise: a central processing device; a communications...
US-6,557,116 Emulation suspension mode with frame controlled resource access
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,557,097 Linear vector computation
A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The...
US-6,556,575 Broadcast traffic reduction in a communications network
The present invention includes a method and system for routing broadcast packets in a network (250) using a switching device (200) which is operable to...
US-6,556,408 Compensation circuit for leakage through electrostatic discharge protection devices
A mixed-signal integrated circuit (12) having compensation for leakage through an ESD cell (16) at an external terminal of a reference voltage is disclosed. A...
US-6,556,088 Phase-locked loop having a stable damping factor
A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second...
US-6,556,087 Fractional frequency division frequency synthesizer having rounded phase control value
In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency...
US-6,556,081 Single-ended, ultra low voltage class AB power amplifier architecture having a common-mode feedback quiescent...
A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control...
US-6,556,077 Instrumentation amplifier with improved AC common mode rejection performance
A method and apparatus for improving the AC common mode rejection performance of monolithic two op-amp instrumentation amplifiers is disclosed. A new approach to...
US-6,555,977 Disk drive motor position detection using mutual inductance zero crossing
The invention includes a method and apparatus for detecting the position of an electric motor rotor by sensing the zero crossing or polarity change of a mutual...
US-6,555,476 Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric
Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively,...
US-6,555,446 Body contact silicon-on-insulator transistor and method
A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly...
US-6,555,431 Method for forming integrated circuit capacitor and memory
A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the...
US-6,555,401 Method of controlling bond process quality by measuring wire bond features
A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond...
US-6,554,395 Print head servo and velocity controller with non-linear compensation
A print head motor control system uses a desired function of print head position versus time and a measured print head position to form an error signal. The...
US-6,554,239 Cradle for connecting two hand-held devices to form a single unit
A cradle for attaching two portable hand-held devices to each other. The cradle holds the devices such that one is substantially atop the other. The cradle has a...
US-6,553,840 Linear displacement sensor apparatus
A linear displacement sensor (10) has a capacitive transducer (24) having a flexible diaphragm (24c) disposed in a housing (12) which also slidingly mounts a...
US-6,553,661 Semiconductor test structure having a laser defined current carrying structure
A test structure that is readily and inexpensively configurable to interface with dies having different bond pad configurations is achieved by providing a blank...
US-6,553,558 Integrated circuit layout and verification method
A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction...
US-6,553,547 Method and system for generating charge sharing test vectors
A method for generating charge sharing test vectors for a circuit generates a first test vector (120) and a second test vector (122). The method provides a test...
US-6,553,542 Semiconductor device extractor for electrostatic discharge and latch-up applications
For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data...
US-6,553,541 Reduced-complexity sequence detection
Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The...
US-6,553,513 Emulation suspend mode with differing response to differing classes of interrupts
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,553,502 Graphics user interface for power optimization diagnostics
A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A...
US-6,553,437 Addressing and communication for multiple-chip optical sensor arrays
A technique for serially controlling an array of optical sensor chips over a pair of signal lines. After broadcasting an initializing reset command to all chips...
US-6,553,332 Method for evaluating process chambers used for semiconductor manufacturing
A process chamber (12) is used for plasma etching of a wafer (21) disposed therein. A gas mixture supplied to the chamber eventually passes through openings (28)...
US-6,553,329 System for mapping logical functional test data of logical integrated circuits to physical representation using...
An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps...
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