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Patent # Description
US-6,555,476 Silicon carbide as a stop layer in chemical mechanical polishing for isolation dielectric
Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively,...
US-6,555,446 Body contact silicon-on-insulator transistor and method
A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly...
US-6,555,431 Method for forming integrated circuit capacitor and memory
A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the...
US-6,555,401 Method of controlling bond process quality by measuring wire bond features
A computerized system and method for inspecting and measuring a ball-shaped wire bond formed by an automated bonder pre-programmed to attach a connecting bond...
US-6,554,395 Print head servo and velocity controller with non-linear compensation
A print head motor control system uses a desired function of print head position versus time and a measured print head position to form an error signal. The...
US-6,554,239 Cradle for connecting two hand-held devices to form a single unit
A cradle for attaching two portable hand-held devices to each other. The cradle holds the devices such that one is substantially atop the other. The cradle has a...
US-6,553,840 Linear displacement sensor apparatus
A linear displacement sensor (10) has a capacitive transducer (24) having a flexible diaphragm (24c) disposed in a housing (12) which also slidingly mounts a...
US-6,553,661 Semiconductor test structure having a laser defined current carrying structure
A test structure that is readily and inexpensively configurable to interface with dies having different bond pad configurations is achieved by providing a blank...
US-6,553,558 Integrated circuit layout and verification method
A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction...
US-6,553,547 Method and system for generating charge sharing test vectors
A method for generating charge sharing test vectors for a circuit generates a first test vector (120) and a second test vector (122). The method provides a test...
US-6,553,542 Semiconductor device extractor for electrostatic discharge and latch-up applications
For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data...
US-6,553,541 Reduced-complexity sequence detection
Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The...
US-6,553,513 Emulation suspend mode with differing response to differing classes of interrupts
Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated...
US-6,553,502 Graphics user interface for power optimization diagnostics
A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A...
US-6,553,437 Addressing and communication for multiple-chip optical sensor arrays
A technique for serially controlling an array of optical sensor chips over a pair of signal lines. After broadcasting an initializing reset command to all chips...
US-6,553,332 Method for evaluating process chambers used for semiconductor manufacturing
A process chamber (12) is used for plasma etching of a wafer (21) disposed therein. A gas mixture supplied to the chamber eventually passes through openings (28)...
US-6,553,329 System for mapping logical functional test data of logical integrated circuits to physical representation using...
An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps...
US-6,553,074 Method and device for combating PCM line impairments
A method and device for combating logarithmic quantization and Robbed Bit Signaling (RBS) impairments that..are typical to PCM telephone lines is descried. An...
US-6,552,923 SRAM with write-back on read
A data storage cell that is stable on standby but upsets on read. Standby stability is achieved without read and restore. In one embodiment, the leakage current...
US-6,552,840 Electrostatic efficiency of micromechanical devices
An improved micromechanical device, particularly a micromirror device having improved electrostatic efficiency. A deflectable member comprised of a mirror 302...
US-6,552,674 Automatic configuration of universal variable length code for video coding
This invention is a method to automatically configure the universal variable length coding (UVLC). The method is applicable to code the syntax elements with a...
US-6,552,673 Efficient table access for reversible variable length code decoding using a hash function
An efficient decoding of reversible variable length codes of the type implemented for H.263++ and MPEG-4 DCT coefficients using lookup tables. Simple-profile...
US-6,552,614 Broadband cable modem amplifier with programmable bias current
An upstream programmable gain amplifier (PGA) (114, 214) for a cable modem (100) having a programmable bias current. PGA (114, 214) includes a bias ...
US-6,552,613 Output stage amplifier with compensation circuitry
An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for...
US-6,552,573 System and method for reducing leakage current in dynamic circuits with low threshold voltage transistors
A reduced-leakage current dynamic circuit (10) is disclosed that includes a logic circuit (30), a pre-charge transistor (32), and a standby transistor (40). The...
US-6,552,566 Logic array circuits using silicon-on-insulator logic
Logic array circuits are formed on SOI substrates. The pull-down network (130) of the logic array circuit comprises NMOS transistors (125) and PMOS transistors...
US-6,552,430 Ball grid array substrate with improved traces formed from copper based metal
A micro-BGA style package for semiconductor device comprises a semiconductor chip and a package substrate. The semiconductor chip includes a plurality of...
US-6,552,388 Hafnium nitride gate dielectric
A field effect semiconductor device comprising a high permittivity hafnium (or hafnium-zirconium) nitride gate dielectric and a method of forming the same are...
US-6,551,943 Wet clean of organic silicate glass films
A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H.sub.2 O.sub.2 is...
US-6,551,904 Method of manufacturing photodiodes
The object of this invention is to provide a method of manufacturing diodes, said method being a method of manufacturing semiconductor devices whereby an...
US-6,550,035 Method and apparatus of Reed-Solomon encoding-decoding
A Reed-Solomon encoding device is provided that can handle multiple RS (Reed-Solomon) codes using different field generation polynomials. The encoding device...
US-6,549,597 High speed phase alignment process and device
A device for phase alignment between a data signal and a main clock signal, characterized by the fact that, from a main clock signal, it has some means of...
US-6,549,584 Coding scheme for cable modems
A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included,...
US-6,549,512 MDSL DMT architecture
A DMT device having an analog front end for receiving an analog signal, a converter for converting the analog signal to a digital signal, a FFT for converting...
US-6,549,357 Selectable input pole compensation for a disk drive read head
A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in...
US-6,549,353 Overshoot control for a hard disk drive write head
An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and...
US-6,549,338 Bandpass filter to reduce thermal impact of dichroic light shift
A color splitting prism assembly (100) comprised of three prisms. Each a dichroic filter at an interface (112) between a first and second of the three prisms...
US-6,549,155 Signal conversion using coarse and fine digital to analog converters
Signal conversion apparatus and method with coarse and fine digital to analog converters. The output of the coarse DAC has a high gain to support wide voltage...
US-6,549,138 Method and apparatus for providing detection of excessive negative offset of a sensor
Detection of excessive negative offset of a condition responsive sensor such as a pressure responsive full Wheatstone bridge element (10) and circuitry...
US-6,549,049 Dynamic voltage reference circuit
A differential pair input receiver (30) having variable reference voltages that may be customized by the designer so as to increase and decrease noise margins of...
US-6,548,997 Mechanism for measurement of time duration between asynchronous events
A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting...
US-6,548,973 Method and apparatus for braking a polyphase DC motor
A circuit (10) for braking a polyphase dc motor (12) includes a circuit (38) for producing an output signal indicating that the motor has slowed at least to an...
US-6,548,942 Encapsulated packaging for thin-film resonators and thin-film resonator-based filters having a piezoelectric...
An acoustic reflector (48) is applied over a thin-film piezoelectric resonator (41, 61) which is supported on a semiconductor or semiconductor-compatible...
US-6,548,924 Protective device for a hermetically sealed type compressor and a hermetically sealed compressor listing same
A protective device (3) for a hermetic type electromotively driven compressor (1a) includes a protector assembly (30) having a housing (32) with an electric...
US-6,548,874 Higher voltage transistors for sub micron CMOS processes
An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS...
US-6,548,841 Nanomechanical switches and circuits
A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its...
US-6,548,400 Method of fabricating interlevel connectors using only one photomask step
A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one...
US-6,548,366 Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a...
US-6,548,362 Method of forming MOSFET with buried contact and air-gap gate structure
A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad...
US-6,548,359 Asymmetrical devices for short gate length performance with disposable sidewall
An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high V.sub.T net dopant adjacent...
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