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Patent # Description
US-6,608,905 Microphone bias current measurement circuit
A microphone bias current detection circuit includes: a microphone circuit 18; an amplifier 10 having a first output and a second output, the first output is...
US-6,608,865 Coding method for video signal based on the correlation between the edge direction and the distribution of the...
The objective of the invention is to make high-efficiency compressed coding for images. In coding of video signals in this application example, the edge is...
US-6,608,821 Method for collision avoidance in an asynchronous communication system
A method of avoiding collisions among a plurality of transmitters that communicate asynchronously in relation to each other with a single receiver. The...
US-6,608,792 Method and apparatus for storing data in an integrated circuit
A circuit (100) for protecting sensitive data stored in a storage area (108) includes a one time programmable device such as a fuse element (104) coupled to the...
US-6,608,521 Pulse width modulation regulator control circuit having precise frequency and amplitude control
A control circuit (50) for a switch mode power converter having precise control of amplitude and frequency that does not exhibit overshoot error nor undershoot...
US-6,608,520 Regulator circuit
To provide a regulator circuit capable of preventing oscillation of output voltage when an overcurrent regulating function is activated voltage across resistor...
US-6,607,985 Gate stack and etch process
A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks...
US-6,606,687 Optimized hardware cleaning function for VIVT data cache
A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX...
US-6,606,686 Unified memory system architecture including cache and directly addressable static random access memory
A data processing apparatus includes a central processing unit and a memory configurable as cache memory and directly addressable memory. The memory is...
US-6,606,590 Emulation system with address comparison unit and data comparison unit ownership arbitration
In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation...
US-6,606,415 Feedback control for hybrid compression
A closed loop feedback system adaptively controls the compression ratio in a Raster Image Processor. The image content is analyzed in real time, and rasterized...
US-6,606,042 True background calibration of pipelined analog digital converters
Systems and methods are provided for performing a background calibration technique on one or more stages of a pipeline Analog-to-Digital Converter (ADC). The...
US-6,606,004 System and method for time dithering a digitally-controlled oscillator tuning input
A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register 1306 and a multiplexer 1308 responsive to a...
US-6,605,859 Buried Zener diode structure and method of manufacture
A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down...
US-6,605,540 Process for forming a dual damascene structure
The invention describes a method for forming a dual damascene structure. An etch stop layer (150) is formed on a dielectric layer (140). A second dielectric...
US-6,605,536 Treatment of low-k dielectric films to enable patterning of deep submicron features
Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H.sub.2 SO.sub.4) to improve patterning. Resist poisoning occurs due to an...
US-6,605,482 Process for monitoring the thickness of layers in a microelectronic device
A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material...
US-6,604,233 Method for optimizing the integrated circuit chip size for efficient manufacturing
The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and,...
US-6,604,154 Data processing device
Deter the lowering of the efficiency of data exchange in a data processing device that conducts data communications by using a serial bus conforming to the IEEF...
US-6,603,412 Interleaved coder and method
Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address...
US-6,603,366 Trimmable oscillator
The present invention relates to a trimmable oscillator circuit which comprises a comparator circuit operable to compare an output voltage of the oscillator...
US-6,603,328 Semiconductor integrated circuit
The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary...
US-6,603,295 Circuit configuration for the generation of a reference voltage
The circuit configuration for the generation of a reference voltage (Vref) contains a reference voltage source (12) and a storage capacitor (C2) to which a...
US-6,602,803 Direct attachment semiconductor chip to organic substrate
A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a...
US-6,602,726 Bond surface conditioning system for improved bondability
Thick film bond surfaces (8) on a support structure (10), such as a ceramic substrate or an IC package substrate, tend to deform during processing. A personality...
US-6,600,466 Method and circuit for controlling contrast in liquid crystal displays using dynamic LCD biasing
A method of controlling contrast in LCDs using dynamic LCD biasing includes the step of identifying an expected bias function as a function of LCD material, LCD...
US-6,600,351 Loop filter architecture
A phase-lock loop (PLL) filter architecture includes a first charge pump (508) and a second change pump (510). The second charge pump (510) operates in opposite...
US-6,600,327 Method of reducing distortion and noise of square-wave pulses, a circuit for generating minimally distorted...
A method and apparatus of measuring current in a switching circuit (2) of the two-port type having a first set of terminals connected to a set of terminals of a...
US-6,600,299 Miller compensated NMOS low drop-out voltage regulator using variable gain stage
A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output NMOS pass device. The voltage regulator uses an...
US-6,600,208 Versatile system for integrated circuit containing shielded inductor
A versatile system for reducing electromagnetic interference resulting from an inductor (300) formed within an integrated circuit is disclosed, including an...
US-6,600,183 Integrated circuit capacitor and memory
An electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier 208 and a bottom electrode comprising a...
US-6,599,829 Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization
An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of:...
US-6,599,802 Low-voltage-Vt (CMOS) transistor design using a single mask and without any additional implants by way of...
Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage....
US-6,598,214 Design method and system for providing transistors with varying active region lengths
A method (40) of designing a circuit comprising a plurality of transistors (10, 46.sub.T, 60.sub.T). Each transistor of the plurality of transistors comprises an...
US-6,598,201 Error coding structure and method
A decimated and interleaved multiplication table for finite fields as is useful in Reed-Solomon encoding computations. The generator polynomial coefficients...
US-6,598,188 Error-corrected codeword configuration and method
Modem selection of Reed-Solomon codeword configuration to maximize error-corrected data rate given channel analysis. A lookup table of maximal codeword size...
US-6,598,151 Stack Pointer Management
A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region (910) is used to pass...
US-6,598,111 Backplane physical layer controller
A system includes a serial bus 330, at least a first portion of which is formed on a circuit board. A first physical layer controller 322 is coupled to the first...
US-6,598,007 Digital control loop
Asynchronous position pulses drive an interrupt to store pulse times via direct memory access; then synchronous sampling and analysis of the stored position...
US-6,597,963 System and method to recreate illumination conditions on integrated circuit bonders
A computerized system and method for recreating illumination conditions in a slave bonder, prepared to attach connecting bonds onto bond pads of a slave...
US-6,597,924 Coupled portable telephone/interface module
The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a...
US-6,597,729 Joint position and carrier frequency estimation method of initial frequency acquisition for a WCDMA mobile terminal
A WCDMA system and method of data communication allows a receiver to reliably achieve carrier frequency acquisition following turn-on without use of temperature...
US-6,597,610 System and method for providing stability for a low power static random access memory cell
A system for providing stability for a low power static random access memory (SRAM) cell (10) is provided that includes a wordline (14), a driver (34) and a mode...
US-6,597,302 System for increasing the bandwidth of sample-and-hold circuits in flash ADCs
An analog-to-digital converter to convert an analog signal to a digital signal, including a sample-and-hold circuit to sample and hold the analog signal and to...
US-6,597,183 Resistance measurement system
A system is provided for precisely measuring a resistive load embedded in a potentially non-linear and capacitive Powered Device network which eliminates...
US-6,597,165 Compare path bandwidth control for high performance automatic test systems
The compare path bandwidth control for high performance automatic test systems provides a standard dual comparator mode with single ended transmission lines for...
US-6,597,065 Thermally enhanced semiconductor chip having integrated bonds over active circuits
An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude...
US-6,597,035 Robust reference sensing cell for flash memory
A robust reference sensing cell for FLASH memory is formed. The cell utilizes floating gate transistors with a drain transition region concentration gradient...
US-6,597,013 Low current blow trim fuse
A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps....
US-6,596,620 BGA substrate via structure
Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via...
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