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Apparatus and method including an efficient data transfer for analog to
digital converter testing
The test system and method described herein reduces the production test time of semiconductor devices. More specifically, the apparatus method in accordance with...
Integrated differential current comparator with input to output electrical
An isolated integrated differential current comparator for comparatively measuring the current passing through one or two resistors using a thermal difference...
LDMOS device with self-aligned RESURF region and method of fabrication
A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable...
Sproutless pre-packaged molding for component encapsulation
A method and apparatus for encapsulating an integrated circuit die and leadframe assembly. A prepackaged sproutless mold compound insert 71 is placed in a...
Method and apparatus for predicting an operational lifetime of a transistor
An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design (10) and a specified set of...
Multiplexer reconfigurable image processing peripheral having for loop
The proposed hardware architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute...
Parallel difference coding method for lossless compression and real time
A block based hybrid compression method where the input page is classified as SOLID, TEXT, SATURATED TEXT or IMAGE type, and the compression method most...
Phase current sensor using inverter leg shunt resistor
In a pulse width modulation controlled three-phase voltage-source inverter having three legs, each leg including two transistors coupled serially between the...
Efficient rendering of masks to a screened buffer using a lookup table
A method and system for expanding a pixel bitmap mask. The pixel bitmap mask (102) is expanded by the use of a lookup table (104) to create an m*n bit expanded...
Method and apparatus for compensation of point noise in CMOS imagers
This invention corrects of white spot noise in an imager. If the brightness value of a pixel is greater than the maximum brightness value of eight surrounding...
Complete CDS/PGA sample and hold amplifier
A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes...
Histogram-based intensity expansion
A method and apparatus for selectively scaling portions of image data based on the intensity levels of historical image data. The selective scaling, or level...
Fast saturation recovery operational amplifier input stage
An operational amplifier input stage includes a first differential input transistor and a second differential input transistor receiving a differential input...
Low-voltage, broadband operational amplifier
A low voltage, broadband differential operational amplifier which eliminates the long tail current source from the amplifier, thereby relieving the headroom...
Dynamic slew-rate booster for CMOS-opamps
The opamp with a slew rate booster includes a first high side transistor 23 coupled to a first differential output node OUT-; a second high side transistor 26...
Integrated circuit and method
An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the...
Ball grid assembly with solder columns
A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel...
Titanium nitride metal interconnection system and method of forming the
A method of fabricating a DRAM integrated circuit structure (30) and the structure so formed, in which a common interconnect material (42, 48) is used as a first...
Integrated circuit interconnect and method
An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide...
Protection of tungsten alignment mark for FeRAM processing
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a...
Methods of preventing reduction of irox during PZT formation by
metalorganic chemical vapor deposition or other...
A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of...
Reconfigurable SIMD coprocessor architecture for sum of absolute
differences and symmetric filtering (scalable...
The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences,...
Data protection system
A method of communicating from a transmitter to a receiver over a communication medium. For the transmitter, the method includes the step of formatting data into...
Demodulation element assignment for a receiver capable of simultaneously
demodulating multiple spread spectrum...
A method (32) of operating a spread spectrum communications receiver (20). The method demodulates a current path group with a demodulator (28), wherein the...
Eliminating power-down popping in audio power amplifiers
The circuit includes: a transistor 22; and a switch 32 coupled to a backgate of the transistor 22 for switching between a power supply node and current-path node...
Gate bootstrapped CMOS sample-and-hold circuit
A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and...
Sample and hold phase detector having low spurious performance and method
A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node (502) to a first voltage level after a...
Semiconductor device and its manufacturing method
Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor...
Integrated circuit wireless tagging
A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an...
Selection of materials and dimensions for a micro-electromechanical switch
for use in the RF regime
The present invention provides an apparatus and method of selecting a unique combination of materials and dimensions for fabrication of a micro-electromechanical...
Method for forming a bottom corner rounded STI
Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded...
Architecture using dedicated endpoints and protocol for creating a
multi-application interface and improving...
A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host,...
Method and architecture to facilitate achieving a fast EPR4 equalization
start-up in a magnetic recording read...
A method and circuit (10) for achieving a fast EPR4 equalization start-up for an FIR filter (14) in a magnetic recording read channel is presented in which a...
Emulation devices, systems and methods utilizing state machines
An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and...
DSL communication system with improved bandwidth
A telecommunications system using DSL modems (36, 38) detects on-hook or off-hook states of a local loop telecommunications line (18). If the local loop (18) is...
Apparatus and method for writing servo patterns on a computer hard disk
A method for writing servo patterns on a hard disk drive disk in a hard disk drive assembly. The assembly includes a disk having at least one magnetic surface in...
Write to read switching time trim circuit
An offset circuit to correct an offset between differential signals includes a read circuit to read the differential signals, a circuit to measure the offset of...
Efficient analog-to-digital converter for digital systems
An analog-to-digital converter 16 includes first and second analog-to-digital converters 22 and 24 both of which receive an input signal. The first...
Hidden hinge digital micromirror device with improved manufacturing yield
and improved contrast ratio
An improved DMD type spatial light modulator having an array of pixels (18). The pixels (18) are of the "hidden hinge" design, each pixel having a mirror (30)...
Digital nonuniformity correction for image sensors
A method of compensating for nonuniformities in an image sensor includes: providing an image sensing device 20; measuring test pixel signals from the image...
Oscillator averaging phase shift generator
Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift...
Phase-locked loop for ADSL frequency locking applications
A phase-locked loop (PLL), particularly useful for ADSL frequency locking applications, uses inexpensive external components in combination with versatile logic...
Process-insensitive, highly-linear constant transconductance circuit
A process-insensitive, highly-linear, constant transconductance circuit employs a CMOS multiplier in the signal path that is offset biased with a specific...
Synchronous coupled inductor switching regulator with improved output
The present invention relates to circuits and method for providing regulated output voltages from an unregulated input voltage. A switching power supply and/or a...
Multiple output switching regulator
A voltage regulator is provided for taking an input voltage and providing a multiple of output voltages of differing voltage values. The voltage regulator...
Scribe street seals in semiconductor devices and method of fabrication
An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing...
Electrostatic discharge resistant extended drain metal oxide semiconductor
A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor...
Repackaging semiconductor IC devices for failure analysis
The present invention provides a system and method for preparing semiconductor integrated circuits ("ICs"), particularly ball grid arrays ("BGAs"), quad flat...
Semiconductor growth method
Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include...
Reduced power testing with equally divided scan paths
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...