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Patent # Description
US-9,590,699 Guided near field communication for short range data communication
A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a...
US-9,590,086 Buffer stack for group IIIA-N devices
A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group...
US-9,589,983 Efficient buried oxide layer interconnect scheme
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried...
US-9,589,959 Compensated well ESD diodes with reduced capacitance
An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance,...
US-9,589,514 Methods and apparatus for reduced bandwidth pulse width modulation
Methods and apparatus for reduced bandwidth pulse width modulation are disclosed. A system includes a digital controller circuit coupled to a data interface,...
US-9,589,093 Multilevel via placement with improved yield in dual damascene interconnection
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer...
US-9,589,005 Method, system and computer program product for storing a decision tree
At least first nodes and second nodes of a decision tree are stored within a memory of an information handling system. The first nodes include a first parent...
US-9,588,566 Programmable time delay and signal polarity improving transceiver signal-to-noise metric
Suppression of interference across transceivers integrated on a single semiconductor chip. An example of a method of reducing noise in a transceiver includes...
US-9,588,178 Parallel and serial data with controller, delay, and register circuits
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-9,584,802 Reducing context coded and bypass coded bins to improve context adaptive binary arithmetic coding (CABAC)...
Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather...
US-9,584,542 Relay attack countermeasure system
An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge...
US-9,584,432 Circular time differencing add/subtract delta to TMAX on sign, MSB
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing...
US-9,584,186 Communications device for multi-tone mask mode operation
A communications device for Multi-Tone Mask (MTM) mode communications at a first router on a powerline communications (PLC) channel in a PLC network including a...
US-9,584,185 Relative phase detection in power line communications networks
Systems and methods for relative phase detection and zero crossing detection for power line communications (PLC) are described. In some embodiments, both...
US-9,584,172 Wireless network receiver
A wireless network receiver includes a detection module that uses preamble data in a data frame for signal processing functions and the detection module is...
US-9,584,115 Duty cycle-controlled load switch
A switch includes a power transistor configured to switch an input voltage to a load. The switch further includes a charge pump and a duty cycle controller. The...
US-9,584,006 System and method for optimizing constant power, constant current and constant voltage operation
A circuit includes a device monitoring component, a voltage error component, a current error component, a power error component, an error selecting component, a...
US-9,583,612 Drift region implant self-aligned to field relief oxide with sidewall dielectric
An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region....
US-9,583,611 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
US-9,583,609 MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal...
Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions...
US-9,583,596 Drain extended CMOS with counter-doped drain extension
An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS...
US-9,583,579 Poly sandwich for deep trench fill
A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon...
US-9,583,558 High breakdown voltage microelectronic device isolation structure with improved reliability
A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low...
US-9,583,488 Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and...
US-9,583,336 Process to enable ferroelectric layers on large area substrates
A microelectronic device with a ferroelectric layer is formed using an MOCVD tool. A substrate is disposed on a susceptor heated to 600.degree. C. to...
US-9,582,021 Bandgap reference circuit with curvature compensation
A bandgap reference circuit with curvature compensation. The circuit includes a first current mirror that mirrors the current conducted by the bandgap...
US-9,581,649 Method and apparatus for load fault detection
Described examples include controllers and methods for controlling an inverter to drive a load and for detecting load faults by determining phasor values...
US-9,581,645 Test circuit providing different levels of concurrency among radio cores
A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table...
US-9,580,304 Low-stress low-hydrogen LPCVD silicon nitride
A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000...
US-9,578,336 Hybrid video and graphics system with automatic content detection process, and other circuits, processes, and...
A computing device (300) includes a storage (325) that over time is operable to include video and graphics content and the storage has a first set of...
US-9,578,325 Drift reduction for quality scalable video coding
This invention is a method of scalable video encoding and decoding. The scalable video encoding codes both a base layer and an enhanced layer having greater...
US-9,577,630 Adaptive system controlled power supply transient filter
An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on...
US-9,577,589 Nonlinear class AB input stage
A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the...
US-9,577,517 Startup clamp circuit for non-complimentary differential pair in DCDC converter system
A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a...
US-9,577,508 NMOS LDO PSRR improvement using power supply noise cancellation
Power-supply ripple rejection (PSRR) at high frequencies is improved for an LDO voltage regulator with an NMOS pass transistor (MN1). A ripple voltage...
US-9,577,185 Fluxgate device with low fluxgate noise
An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal...
US-9,577,094 Low cost demos transistor with improved CHC immunity
An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that...
US-9,577,033 Trench gate trench field plate vertical MOSFET
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the...
US-9,576,886 Flat no-lead packages with electroplated edges
A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet...
US-9,576,804 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,576,643 Array power supply-based screening of static random access memory cells for bias temperature instability
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory...
US-9,576,621 Read-current and word line delay path tracking for sense amplifier enable timing
A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM...
US-9,576,540 Operating an electrophoretic display with first and second operating formats
Electrophoretic displays (EPDs) and methods for controlling EPDs are disclosed herein. An embodiment of an EPD includes a first operating format, wherein pixels...
US-9,576,333 Data processing system and method thereof
Several systems and methods for data processing are disclosed. In an embodiment, a data processing system includes a host processor, a plurality of slave...
US-9,575,901 Programmable address-based write-through cache control
This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a...
US-9,575,619 Data capture design tool for designing and configuring systems with analog front ends
A method of configuring a system includes a selectable analog output device and an analog front end (AFE). The method includes selecting, via a graphical user...
US-9,575,473 Back EMF monitor for motor control
An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference...
US-9,575,014 Material determination by sweeping a range of frequencies
A material-discerning device is arranged to include an antenna, a proximity sensor, a band pass filter and a processor. The antenna radiates a radio-frequency...
US-9,573,801 MEMS electrostatic actuator device for RF varactor applications
A MEMs actuator device and method of forming includes arrays of actuator elements. Each actuator element has a moveable top plate and a bottom plate. The top...
US-9,572,261 Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips
An electronic system comprising an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor...
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