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Patent # Description
US-9,601,995 Low power radio frequency envelope detector
A low power radio frequency envelope detector includes a charging transistor for controlling the charge supplied to an output capacitor. A first input capacitor...
US-9,601,820 Dielectric waveguide comprised of a core surrounded by a cladding and forming integrated periodical structures
A dielectric waveguide interconnect system has a dielectric waveguide (DWG) a core surrounded by a cladding along the length of the DWG. One or more periodic...
US-9,601,819 Dielectric waveguide with extending connector and affixed deformable material
A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a...
US-9,601,612 MOSFET having dual-gate cells with an integrated channel diode
A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region....
US-9,601,414 Method for preventing die pad delamination
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a...
US-9,601,225 Multiple-cavity vapor cell structure for micro-fabricated atomic clocks, magnetometers, and other devices
An apparatus includes a vapor cell having multiple cavities fluidly connected by one or more channels. At least one of the cavities is configured to receive a...
US-9,601,152 Additional overshoot current HDD write driver circuit
A hard disk drive write drive method and integrated circuit that provide a configurable overshoot current based on the length of the pattern in the write...
US-9,601,123 Undetectable combining of nonaligned concurrent signals
The approach shown provides for an efficient implementation of time response, level response and frequency response alignment between two audio sources such as...
US-9,600,239 Cryptographic accelerator
A cryptographic accelerator performs various modular arithmetic operations producing unreduced results bounded by the double of the modulus (i.e.: 2*M). In...
US-9,599,975 Sensor synchronized networks using overlapping sensor fields
A method of synchronizing includes providing a sensor network including sensor nodes having object recognition sensors (ORS's) and building automation network...
US-9,599,739 Material-discerning sensing by measurement of different points of impedance
A material-discerning proximity sensor is arranged to include an antenna that is arranged to radiate a radio-frequency signal. A capacitive sensor is arranged...
US-9,599,669 Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access...
US-9,599,668 Addressable tap domain selection circuit, interface select and instruction circuitry
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-9,596,724 Method and apparatus for calculating an average value of an inaccessible current from an accessible current
In a power converter, a circuit determines an average value of an inaccessible current from an average value of an accessible current and a value of the...
US-9,596,558 Wireless sensor network and association request transmission method
A method of transmitting association requests in a wireless sensor network includes transmitting an association request from a leaf node to an intermediate...
US-9,596,325 Data frame for PLC having destination address in the PHY header
A physical layer (PHY) data frame for use in conjunction with processor in a node, processor coupled to a program memory for storing a sequence of operating...
US-9,596,111 Methods and apparatus for multi-channel modem and preamble detection
Methods and apparatus for multiple channel modem and preamble detection. In an example arrangement, a system includes a plurality of communication nodes coupled...
US-9,596,008 Method and apparatus for die-to-die communication
In apparatus for die-to-die communication, a first die includes at least a first circuit, and a second die includes at least a second circuit. The first die is...
US-9,595,937 Programmable step attenuator with cross connection
Disclosed examples include a programmable attenuator circuit providing selective cross coupling of impedance components between circuit input nodes and output...
US-9,595,929 Distributed pole-zero compensation for an amplifier
An amplifier includes an amplifier input and an amplifier output. A compensation network is coupled to the amplifier output. The compensation network includes...
US-9,595,875 Voltage converter compensation apparatus and methods
On the secondary side of a flyback switching power converter, a compensation diode and a voltage divider with an averaging circuit generate an output...
US-9,595,871 High efficiency inductive capacitive DC-DC converter
Disclosed examples include high-efficiency integrated circuits and inductive capacitive DC-DC converters with a first converter stage including first and second...
US-9,595,867 System and method to improve standby efficiency of LLC converter
A system includes an LLC converter to convert an input DC voltage to an output DC voltage. A burst generator generates a switching signal having a burst time...
US-9,595,480 Method of forming a BICMOS semiconductor chip that increases the betas of the bipolar transistors
The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a...
US-9,594,388 Digital shunt regulator for NFC devices
A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak...
US-9,594,387 Voltage regulator stabilization for operation with a wide range of output capacitances
A voltage regulator includes a measurement circuit for obtaining a value representing a magnitude of an output capacitance connected at an output node of the...
US-9,594,159 2-D object detection in radar applications
A set of radar data is organized as a two dimensional (2D) array with multiple lines of data. A 2D cross point analysis is performed on each set of data to...
US-9,594,116 IC die with channel circuitry, scan and BIST taps, TLM
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-9,591,320 Context and bypass encoding video
A method and apparatus for encoding and decoding video data. Including context encoding or decoding at least two bins of each significant transform coefficient...
US-9,591,312 Memory bandwidth reduction for motion compensation in video coding
Motion compensation requires a significant amount of memory bandwidth, especially for smaller prediction unit sizes. The worst case bandwidth requirements can...
US-9,590,764 LTE transmission mask adjustment to maximize performance and reduce interference
System and methods for using channel quality reports to reduce inter-band interference are disclosed. Channel information is received at a first wireless...
US-9,590,699 Guided near field communication for short range data communication
A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a...
US-9,590,086 Buffer stack for group IIIA-N devices
A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group...
US-9,589,983 Efficient buried oxide layer interconnect scheme
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried...
US-9,589,959 Compensated well ESD diodes with reduced capacitance
An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance,...
US-9,589,514 Methods and apparatus for reduced bandwidth pulse width modulation
Methods and apparatus for reduced bandwidth pulse width modulation are disclosed. A system includes a digital controller circuit coupled to a data interface,...
US-9,589,093 Multilevel via placement with improved yield in dual damascene interconnection
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer...
US-9,589,005 Method, system and computer program product for storing a decision tree
At least first nodes and second nodes of a decision tree are stored within a memory of an information handling system. The first nodes include a first parent...
US-9,588,566 Programmable time delay and signal polarity improving transceiver signal-to-noise metric
Suppression of interference across transceivers integrated on a single semiconductor chip. An example of a method of reducing noise in a transceiver includes...
US-9,588,178 Parallel and serial data with controller, delay, and register circuits
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus....
US-9,584,802 Reducing context coded and bypass coded bins to improve context adaptive binary arithmetic coding (CABAC)...
Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather...
US-9,584,542 Relay attack countermeasure system
An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge...
US-9,584,432 Circular time differencing add/subtract delta to TMAX on sign, MSB
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing...
US-9,584,186 Communications device for multi-tone mask mode operation
A communications device for Multi-Tone Mask (MTM) mode communications at a first router on a powerline communications (PLC) channel in a PLC network including a...
US-9,584,185 Relative phase detection in power line communications networks
Systems and methods for relative phase detection and zero crossing detection for power line communications (PLC) are described. In some embodiments, both...
US-9,584,172 Wireless network receiver
A wireless network receiver includes a detection module that uses preamble data in a data frame for signal processing functions and the detection module is...
US-9,584,115 Duty cycle-controlled load switch
A switch includes a power transistor configured to switch an input voltage to a load. The switch further includes a charge pump and a duty cycle controller. The...
US-9,584,006 System and method for optimizing constant power, constant current and constant voltage operation
A circuit includes a device monitoring component, a voltage error component, a current error component, a power error component, an error selecting component, a...
US-9,583,612 Drift region implant self-aligned to field relief oxide with sidewall dielectric
An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region....
US-9,583,611 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
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