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Packet processing VLIW action unit with or-multi-ported instruction memory
An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each...
Local oscillator phase noise tracking for single carrier transmission
A system and method for tracking noise in a received signal uses a forward/backward Decision-Directed Phase Tracking Loop to generate a phase-noise compensation...
Supply-state-enabled level shifter interface circuit and method
An enable circuit receives an input enable signal that is referenced to a first voltage and generates a level-shifted output enable signal referenced to a...
LLC converter and loss of inductive mode detection circuit
Methods, control apparatus and series resonant or LLC power conversion systems are presented in which a resonant series circuit current is compared with a...
Non-volatile anti-fuse with consistent rupture
In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable...
Method and structure of packaging semiconductor devices
A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear...
Dominant speech extraction in the presence of diffused and directional
A method of dominant speech extraction is provided that includes acquiring a primary audio signal from a microphone and at least one additional audio signal...
Method and system for lossless value-location encoding
A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct...
Method and system for active noise cancellation
From at least a first microphone, first microphone signals are received that represent first sound waves. From at least a second microphone, second microphone...
Projector-camera misalignment correction for structured light systems
A method of misalignment correction in a structured light device is provided that includes extracting features from a first captured image of a scene, wherein...
Integrated receiver and ADC for capacitive touch sensing apparatus and
An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta...
Dynamic low power states characterization
An optimal idle state of a processor is selected using dynamically derived parameters. For example, the idle state is selected from a group of possible idle...
Vibration and dynamic acceleration sensing using capacitors
The present disclosure relates to an apparatus comprising at least one sensing capacitor and a controller, wherein the controller is configured to receive a...
Method and system for determining proximity of an object
A first sensor detects whether an object is within a first region that surrounds the first sensor. A second sensor detects whether the object is within a second...
A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending...
LED bypass and control circuit for fault tolerant LED systems
A light system (FIG. 2) is disclosed. The light system includes a plurality of series connected light emitting diodes (240-246). Each of a plurality of...
Best-effort scheduled access
Embodiments of the invention provide a best-effort scheduled access method and system that enable nodes to request, and a hub to assign, tentative, but not...
Building, transmitting, and receiving frame structures in power line
Systems and methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described...
Enhanced resolution successive-approximation register analog-to-digital
converter and method
An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC),...
Tunable frequency-to-voltage controlled oscillation
A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a...
Back electromagnetic force (BEMF) sense system
One embodiment includes a back-electromagnetic force (BEMF) sense system. The system includes a sense amplifier configured to measure an amplitude of a selected...
Method and system for converting a DC voltage
An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto....
Cost effective low pin/ball count level-shifter for LCD bias applications
supporting charge sharing of gate...
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load...
An apparatus for rotating a load about a predetermined rotation axis of the apparatus. The apparatus includes a rotatable shaft having a central longitudinal...
Wireless mobile device network application proxy with exchange sequence
Systems and methods disclosed herein receive a network application proxy (NAP)-extended API function call issued by a networking-aware host application. The...
Temporal motion data candidate derivation in video coding
A method for derivation of a temporal motion data (TMD) candidate for a prediction unit (PU) in video encoding or video decoding is provided. The derived TMD...
Digital shunt regulator for NFC devices
A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak...
Controling Tx/Rx mode in serial half-duplex UART separately from host
Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the...
Built-in test system and method
A communication device includes a DC input component, a transmitting component an envelope detecting component, a receiving component, a storage component and a...
Apparatus and method for multilevel coding in communication systems
A method includes receiving input blocks each having multiple bits to be transmitted. The method also includes applying a first encoding scheme to a first...
Integrated clock gating cell using a low area and a low power latch
The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that...
Integrated resonator with a mass bias
An integrated resonator apparatus includes a piezoelectric resonator and an acoustic Bragg reflector formed adjacent the piezoelectric resonator. The integrated...
Apparatus and method for testing of successful operation of transimpedance
The present disclosure relates to an apparatus comprising at least two operational amplifiers, a first and a second current input, at least one voltage output,...
Dynamic mixed-mode current decay apparatus and methods
Stepper motor winding current regulation methods and apparatus continuously and bi-directionally sense winding current to determine both the magnitude of the...
MOS transistor device in common source configuration
A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the...
High voltage multiple channel LDMOS
An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a...
MOSFET with curved trench feature coupling termination trench to active
A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality...
Recessed channel insulated-gate field effect transistor with self-aligned
gate and increased channel length
A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the...
Self aligned active trench contact
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill...
Methods and apparatus to reduce semiconductor wafer warpage in the
presence of deep cavities
Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated...
Die with separate functional input, test out, enable input buffers
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
Deep collector vertical bipolar transistor with enhanced gain
An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base...
Adaptive encoding of a digital signal with one or more missing values
A method of encoding samples in a digital signal is provided that includes receiving a plurality of samples of the digital signal, and encoding the plurality of...
First de-compressing first compressing schemes for pixels from/to bus
A multimedia system includes a processor coupled to a memory, a three-dimensional (3D) graphics engine to generate 3D graphics content, and a display controller...
Zero cycle clock invalidate operation
A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU...
Debug trace stream timestamping using downstream correlation
A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a...
Method for generating descriptive trace gaps
A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and...
Instruction register delay select outputs to clock delay circuitry
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
Interposer with extruded feed-through vias
A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded...
Wireless router system
Conventional routers employ a wired backplane that employs "long reach" serializer/deserializer (SerDes) links, but this type of architecture is complicated,...