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Patent # Description
US-9,276,566 Dual edge-triggered retention flip-flop
A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For...
US-9,276,475 Switched mode assisted linear regulator with decoupled output impedance and signal path bandwidth
A switched mode assisted linear (SMAL) amplifier/regulator architecture can be configured to supply regulated power to a dynamic load, such as an RF power...
US-9,276,056 Baluns for RF signal conversion and impedance matching
A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary...
US-9,276,012 Method to match SOI transistors using a local heater element
An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for...
US-9,275,988 Schottky diodes for replacement metal gate integrated circuits
An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to...
US-9,275,983 Integrated circuit package
A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a...
US-9,275,747 Integrated circuit with automatic total ionizing dose (TID) exposure deactivation
Integrated circuits and methods for deactivating user circuit operation with one or more wide channel sensing transistors biased to an on condition for exposure...
US-9,275,704 Method and apparatus for asynchronous FIFO circuit
The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory...
US-9,274,602 Haptic actuator controller
An apparatus and method for controlling a haptic actuator. A haptic actuator controller can includes driver input amplifier, an actuator feedback amplifier, an...
US-9,274,201 Automatic calibration method for active and reactive power measurement
A system is provided for calibrating a device. The system includes a reference component, a sampling component, a calibration component, a comparing component...
US-9,272,302 Mixing apparatus for mixing bonding adhesive at die bonder before dispense
A moveable dispenser assembly including is shown. The dispenser includes a reservoir having bonding adhesive therein including particles and a liquid carrier....
US-9,271,007 System and method for adaptively allocating resources in a transcoder
An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of...
US-9,270,410 MIMO PGRC system and method
A method of transmitting a wireless signal (FIGS. 3A-3C) is disclosed. A data stream is divided (306) into a first data stream and a second data stream. The...
US-9,270,378 CML output driver
An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input...
US-9,270,349 Downlink 8 Tx codebook sub-sampling for CSI feedback
This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook...
US-9,270,334 Advanced switch node selection for power line communications network
An algorithm for the promotion of terminal nodes to switch nodes in a PLC network reduces overall network overhead and collisions, while ensuring the...
US-9,270,293 System and method for multi channel sampling SAR ADC
A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a...
US-9,270,273 Level shifter
A level shifter is provided. This level shifter includes a first driver, a second driver, a capacitor, and a common mode circuit. The first driver has a first...
US-9,270,257 Dual-port positive level sensitive reset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is...
US-9,270,226 Noninvasive monitoring of a photovoltaic system
A method for determining a photovoltaic (PV) current from each of a plurality of PV elements arranged in a differential network is provided. The differential...
US-9,270,220 Circuits and methods of determining position and velocity of a rotor
A motor controller includes a square wave voltage generator and adding circuitry for adding the square wave voltage to a first drive voltage that is connectable...
US-9,270,180 DC-DC converter with adaptive minimum on-time
A DC-DC converter has a high-side transistor series with a low-side transistor and an inductor connected to a node therebetween, a gate driver circuit has a...
US-9,269,703 ESD protection using diode-isolated gate-grounded nMOS with diode string
An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a...
US-9,269,663 Single pattern high precision capacitor
An integrated circuit contains a high precision capacitor having a bottom plate, a dielectric layer over the bottom plate, a capacitor opening in the dielectric...
US-9,269,636 High quality dielectric for hi-k last replacement gate transistors
A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the...
US-9,268,895 Circuit design synthesis tool with export to a computer-aided design format
A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input...
US-9,268,708 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain...
This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines....
US-9,268,350 Power management apparatus with rapid short response and full load recovery
A voltage feedback loop employed with a power distribution switch rapidly responds to a predetermined drop in output voltage to increase the resistance of the...
US-9,267,990 CLK/TMS counter having reset output coupled to fourth count output
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path....
US-9,267,829 Single transceiver ultrasonic flow meter having an array of transducer elements
Elements of a single beam-forming array of ultrasonic transducer elements are selectively activated to direct two or more ultrasonic beams to a series of...
US-9,264,710 Method and system for video picture intra-prediction estimation
Several systems and methods for intra-prediction estimation of video pictures are disclosed. In an embodiment, the method includes accessing four `N.times.N`...
US-9,264,679 Maintaining distortion-free projection from a mobile device
A mobile device, such as a smart phone, is provided with a camera and a projector. A user may select a still image or a video sequence and project it onto a...
US-9,264,217 Clock drift compensation applying paired clock compensation values to buffer
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming...
US-9,264,117 Rank and PMI in download control signaling for uplink single-user MIMO (UL SU-MIMO)
A method of operating a user equipment device includes extracting at least one rank indicator (RI) from an uplink grant, and adapting a transmission rank in...
US-9,264,103 Asymmetric channels in power line communications
Apparatus (and related methods) for a power line communication network include a processor configured to receive beacons over a communication interface. The...
US-9,264,038 Line receiver circuit with active termination
A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input...
US-9,263,973 MEMS electrostatic actuator
A MEMS electrostatic actuator includes a bottom plate affixed to a substrate and a top plate suspended above the bottom plate. The top plate has a parallel...
US-9,263,952 Fast high-side power FET gate sense circuit for high voltage applications
A circuit for sensing gate voltage of a power FET. A switching circuit includes a switching FET having a high voltage rating, its drain coupled to the gate of...
US-9,263,444 Devices having inhomogeneous silicide schottky barrier contacts
A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided having a...
US-9,263,147 Method and apparatus for concurrent test of flash memory cores
An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module...
US-9,261,764 Optically efficient polarized projector
A pixel array display system which has an illumination source with a plurality of emitters in a sparse array, collimators in front of the emitters, a condenser...
US-9,261,571 Fluxgate magnetic sensor readout apparatus
Compact, low power fluxgate magnetic sensor readout circuits and apparatus are presented in which demodulator or rectifier circuit to modulates a sense signal...
US-9,261,560 Handling slower scan outputs at optimal frequency
An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M...
US-9,261,559 IC tap with dual port router and additional update input
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test...
US-9,261,558 Interposer monitor coupled to clock, start, enable of monitor trigger
The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital...
US-9,258,829 System and method for collision rate reduction in MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,258,783 Access and power management for centralized networks
A system and method for managing power in a subnet having a hub in communication with one or more nodes is disclosed. The hub and nodes communicate using one or...
US-9,258,703 Method, system and computer program product for wirelessly connecting a device to a network
A device wirelessly receives first and second identifiers contemporaneously from a network. The first identifier indicates that the network operates in a first...
US-9,258,224 Packet processing VLIW action unit with or-multi-ported instruction memory
An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each...
US-9,258,107 Local oscillator phase noise tracking for single carrier transmission
A system and method for tracking noise in a received signal uses a forward/backward Decision-Directed Phase Tracking Loop to generate a phase-noise compensation...
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