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Patent # Description
US-9,385,187 High breakdown N-type buried layer
A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low...
US-9,385,140 Efficient buried oxide layer interconnect scheme
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried...
US-9,385,117 NPN heterojunction bipolar transistor in CMOS flow
An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the...
US-9,385,044 Replacement gate process
An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer...
US-9,384,850 OTP read sensor architecture with improved reliability
Circuits and methods for reading an OTP memory cell with improved reliability. To read a first OTP memory cell, a first current amount generated by a second,...
US-9,384,826 Circuits and methods for performance optimization of SRAM memory
In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in...
US-9,384,726 Feedback microphones encoder modulators, signal generators, mixers, amplifiers, summing nodes
A noise-cancelling system includes headset for generating a feedback signal for noise-cancellation in response to sound externally generated from the headset....
US-9,384,109 Processor with debug pipeline
A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution...
US-9,384,003 Determining whether a branch instruction is predicted based on a capture range of a second instruction
An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU)...
US-9,383,761 Apparatus and method for multiphase SMPS interleaving
In described examples, a phase interleaver obtains (i) a first signal indicating a variance between a reference voltage and a regulated output voltage and (ii)...
US-9,383,586 Stereoscopic imaging systems utilizing solid-state illumination and passive glasses
A stereoscopic display system employs narrowband illumination light beams and passive glasses with built-in interference filters. The system is also compatible...
US-9,383,418 Integrated dual axis fluxgate sensor using double deposition of magnetic material
A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core...
US-9,383,410 Inverted TCK access port selector having resets selecting one tap
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
US-9,383,403 TSVs connected to ground and combined stimulus and testing leads
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the...
US-9,383,393 Dual-comparator circuit with dynamic VIO shift protection
A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary...
US-9,383,209 Undocking and re-docking mobile device inertial measurement unit from vehicle
According to an aspect of the present disclosure, the relative attitude between an inertial measurement unit (IMU), present on a mobile device, and the frame of...
US-9,382,022 Packing insert for disc-shaped objects
A packing insert for disc-shaped objects comprising a ring and a deformable contacting portion supported by the ring and extending from a circumference of the...
US-9,380,314 Pixel retrieval for frame reconstruction
A video decoder receives data representing an encoded image frame partitioned into one or more partitions. The video decoder stores the motion vector associated...
US-9,380,302 Sample adaptive offset (SAO) parameter signaling
Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream...
US-9,380,260 Multichannel video port interface using no external memory
This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high...
US-9,379,904 Enhanced carrier sense multiple access (CSMA) protocols
Power Line Communications (PLC) device for enhanced carrier sense multiple access (CSMA) protocols are described. The PLC device includes a modem, an AC...
US-9,379,774 System for transmitting information between circuits
A system for transferring information from a first circuit to a second circuit includes first and second isolation elements coupled between the first circuit...
US-9,379,773 Phase detection in power line communication systems
Phase detection between service nodes in a as "PRIME" ("PoweRline Intelligent Metering Evolution") communications network, in which the service nodes are...
US-9,379,746 Isolation circuits for digital communications and methods to provide isolation for digital communications
Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes...
US-9,379,540 Controllable circuits, processes and systems for functional ESD tolerance
An electronic circuit (100) includes a first circuit (140) having an output and operable to give a warning but that has a sensitivity to an electrostatic...
US-9,379,176 Well resistors and polysilicon resistors
An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled...
US-9,379,087 Method of making a QFN package
A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and...
US-9,379,022 Process for forming driver for normally on III-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
US-9,378,984 Packaging a semiconductor device having wires with polymerized insulator skin
A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with...
US-9,378,882 Method of fabricating an electronic circuit
Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a...
US-9,378,848 Methods and devices for determining logical to physical mapping on an integrated circuit
Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes...
US-9,378,185 Transform and quantization architecture for video coding and decoding
A method of encoding a video stream in a video encoder is provided that includes computing an offset into a transform matrix based on a transform block size,...
US-9,378,177 WiFi USB protocol
A wireless universal serial bus (USB) system that includes a wireless USB host, a first wireless USB device, and a second wireless USB device. The wireless USB...
US-9,377,509 Core wrapper link instruction register controls responsive to select signal
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
US-9,374,831 Network coexistence through active superframe interleaving
Embodiments of the invention provide coexistence among independent networks through active superframe interleaving. Network hubs and devices exchange signals...
US-9,374,678 Kalman filter iteratively performing time/measurement update of user/relative floor locations
Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless...
US-9,374,592 Mode estimation in pipelined architectures
A video system includes an encoder for generating a compressed bit stream in response to a received video signal. The encoder includes a mode decision processor...
US-9,374,444 Frame structure for medium access in body area networks (BAN)
A system and method for providing a variety of medium access and power management methods are disclosed. A defined frame structure allows a hub and a node to...
US-9,374,112 Capture selection for digital pre-distortion adaptation and capture concatenation for frequency hopping...
A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a...
US-9,374,064 Micro-step resistance networks
A series-structure, parallel-structure and combined structure of micro-step resistance network circuits is disclosed. Micro-step resistance is maintained, while...
US-9,374,009 Circuits and methods for constant output current in a flyback converter
Flyback converters are disclosed herein. An embodiment of a flyback converter includes a transformer having a primary side and a secondary side. A switch is...
US-9,373,878 Dielectric waveguide with RJ45 connector
A communication cable includes a dielectric wave guide (DWG) that has a dielectric core member that has a first dielectric constant value and a cladding...
US-9,373,615 Bipolar transistor including lateral suppression diode
A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a...
US-9,373,572 Semiconductor package having etched foil capacitor integrated into leadframe
A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and...
US-9,373,571 Integrating multi-output power converters having vertically stacked semiconductor chips
An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first...
US-9,373,569 Flat no-lead packages with electroplated edges
A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad,...
US-9,372,817 High perfomance DMA controller for video processors
This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and...
US-9,372,808 Deadlock-avoiding coherent system on chip interconnect
This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked...
US-9,372,799 Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a...
US-9,372,796 Optimum cache access scheme for multi endpoint atomic access in a multicore system
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
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