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Die attach pick error detection
Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during...
IC die top, bottom signals, tap lock, test, scan circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
Decompressed scan chain masking circuit shift register with log2(n/n)
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to...
Hermetic plastic molded MEMS device package and method of fabrication
A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110)...
Channel selection in power line communications
Systems for channel selection in power line communications (PLC) are described. In some embodiments, a PLC device may include a processor and a memory. The...
Coupler to launch electromagnetic signal from microstrip to dielectric
A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core...
Making a flip-chip assembly with bond fingers
A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally...
Packaged semiconductor devices having solderable lead surfaces exposed by
grooves in package compound
A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the...
Hydrogen passivation of integrated circuits
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping...
Error prediction in logic and memory devices
Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering...
Method and apparatus for secure mode indication
A method and apparatus for a hand-held device for ensuring a secured mode transition. The method includes receiving a request to transition to a mode,...
Adaptive bus termination apparatus and methods
Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor...
Comparator multiplexing LDO and converted output to DC-DC converter
A DC-DC converter receives input power from a power source and generates a regulated DC voltage as an output. The DC-DC converter contains multiple blocks, each...
Method for preventing die pad delamination
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a...
Integrating multi-output power converters having vertically stacked
A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical...
IC rectangular inductor with perpendicular center and side shield traces
An inductive device is provided, which includes a substrate, a layer having a plurality of conductive metal traces and a metal shield layer. The conductive...
Flexible arbitration scheme for multi endpoint atomic accesses in
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
Circuit for detecting and correcting timing errors
A circuit for detecting and correcting timing errors. A timing circuit includes an interpolator. The interpolator includes a fine counter, a coarse counter, and...
Addressable tap address, state monitor, decode and TMS gating circuitry
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
Operating state machine from reset to poll in to reset
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
System and method for testing an electronic device
Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip...
Systems and methods of driving multiple outputs
Systems and methods of driving multiple outputs are provided in which a single inductor may be used to drive multiple output such as independent strings of LEDs...
SerDes communications with retiming receiver supporting link training
A SerDes corn link with a retiming receiver is operable in link training (LT) mode. A SerDes transmitter includes a TX FIR channel driver to transmit TX Data...
Method and circuitry for transmitting data
Data transfer devices and methods for transferring data between first and second circuits are disclosed. A data transfer device includes a first circuit having...
Circuits and methods for cancelling nonlinear distortions in pulse width
A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input...
Combined input stage for transconductance amplifier having gain linearity
over increased input voltage range
First and second transconductance amplifier input stages having first and second gain characteristics, respectively, are combined. The resulting combined input...
Magnetic sensing technique for power supply systems
One embodiment includes a power supply system including a transformer comprising a primary, secondary, and auxiliary winding that are magnetically coupled. The...
Systems and methods of direct cell attachment for batteries
Embodiments of the systems and methods of direct cell attachment for battery cells disclosed herein operate without the protection FETs and the protection IC,...
SRAM well-tie with an uninterrupted grated first poly and first contact
patterns in a bit cell array
An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as...
Bitline leakage detection in memories
An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay...
Universal test structures based SRAM on-chip parametric test module and
methods of operating and testing
An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and...
Read margin measurement in a read-only memory
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of...
Adaptive weighted-local-difference order statistics filters
A novel modification to the order statistics filters called the Adaptive Weighted-Local-Difference Order Statistics is shown that will act as a generic...
Multi-processor, multi-domain, multi-protocol cache coherent speculation
aware shared memory controller and...
This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous...
First/second die, channel interfaces, TAPs, and TLMs with common clock
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
Testing integrated circuit packaging for shorts
An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more...
Coexistence of wireless sensor networks with other wireless networks
A wireless device includes a wireless transceiver configured to transmit to and receive from nodes in a wireless sensor network (WSN) and control logic coupled...
Video compression searching reference frame in hybrid growing-window and
A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of...
Network throughput using multiple reed-solomon blocks
Embodiments of methods and systems are presented for generating PHY frames with multiple Reed-Solomon encoded blocks in PLC networks. In one embodiment, a MAC...
Wireless network with power aware transmission control
A wireless device that tailors communications based on power parameters of the device. In one embodiment, a wireless device includes an energy source, a power...
Automatic gain control for power line communication
A system includes an analog front end (AFE) unit to be coupled to a power line network, and a controller coupled to the AFE unit. More specifically, the AFE...
Primary side current regulation on LLC converters for LED driving
An LLC converter having a bridge circuit coupled to an input voltage at least one pair of power switches, a resonant network, coupled to the bridge circuit and...
Inductor-based active balancing for batteries and other power supplies
A system includes multiple power supplies connected in series and an active balancing circuit. The active balancing circuit includes an LC resonance circuit and...
Low cost demos transistor with improved CHC immunity
An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that...
Methods to enhance effective work function of mid-gap metal by
incorporating oxygen and hydrogen at a low...
A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work...
Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
Well resistors and polysilicon resistors
An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled...
Integration of analog transistor
An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of...
Integrated circuit package with die attach paddle having at least one
An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle....
High voltage depletion mode N-channel JFET
An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through...