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Patent # Description
US-9,252,800 Enhanced resolution successive-approximation register analog-to-digital converter and method
An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC),...
US-9,252,792 Tunable frequency-to-voltage controlled oscillation
A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a...
US-9,252,691 Back electromagnetic force (BEMF) sense system
One embodiment includes a back-electromagnetic force (BEMF) sense system. The system includes a sense amplifier configured to measure an amplitude of a selected...
US-9,252,663 Method and system for converting a DC voltage
An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto....
US-9,251,753 Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate...
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load...
US-9,248,536 Turntable
An apparatus for rotating a load about a predetermined rotation axis of the apparatus. The apparatus includes a rotatable shaft having a central longitudinal...
US-9,247,372 Wireless mobile device network application proxy with exchange sequence generator
Systems and methods disclosed herein receive a network application proxy (NAP)-extended API function call issued by a networking-aware host application. The...
US-9,247,266 Temporal motion data candidate derivation in video coding
A method for derivation of a temporal motion data (TMD) candidate for a prediction unit (PU) in video encoding or video decoding is provided. The derived TMD...
US-9,246,552 Digital shunt regulator for NFC devices
A digital shunt regulator receives a radio frequency (RF) signal at an antenna which generates a differential output signal over a differential path. A peak...
US-9,246,534 Controling Tx/Rx mode in serial half-duplex UART separately from host
Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the...
US-9,246,530 Built-in test system and method
A communication device includes a DC input component, a transmitting component an envelope detecting component, a receiving component, a storage component and a...
US-9,246,510 Apparatus and method for multilevel coding in communication systems
A method includes receiving input blocks each having multiple bits to be transmitted. The method also includes applying a first encoding scheme to a first...
US-9,246,489 Integrated clock gating cell using a low area and a low power latch
The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that...
US-9,246,467 Integrated resonator with a mass bias
An integrated resonator apparatus includes a piezoelectric resonator and an acoustic Bragg reflector formed adjacent the piezoelectric resonator. The integrated...
US-9,246,450 Apparatus and method for testing of successful operation of transimpedance amplifiers
The present disclosure relates to an apparatus comprising at least two operational amplifiers, a first and a second current input, at least one voltage output,...
US-9,246,424 Dynamic mixed-mode current decay apparatus and methods
Stepper motor winding current regulation methods and apparatus continuously and bi-directionally sense winding current to determine both the magnitude of the...
US-9,246,355 MOS transistor device in common source configuration
A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the...
US-9,245,998 High voltage multiple channel LDMOS
An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a...
US-9,245,994 MOSFET with curved trench feature coupling termination trench to active trench
A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality...
US-9,245,975 Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the...
US-9,245,894 Self aligned active trench contact
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill...
US-9,245,855 Methods and apparatus to reduce semiconductor wafer warpage in the presence of deep cavities
Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated...
US-9,245,812 Die with separate functional input, test out, enable input buffers
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
US-9,245,755 Deep collector vertical bipolar transistor with enhanced gain
An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base...
US-9,245,529 Adaptive encoding of a digital signal with one or more missing values
A method of encoding samples in a digital signal is provided that includes receiving a plurality of samples of the digital signal, and encoding the plurality of...
US-9,245,491 First de-compressing first compressing schemes for pixels from/to bus interface
A multimedia system includes a processor coupled to a memory, a three-dimensional (3D) graphics engine to generate 3D graphics content, and a display controller...
US-9,244,837 Zero cycle clock invalidate operation
A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU...
US-9,244,806 Debug trace stream timestamping using downstream correlation
A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a...
US-9,244,805 Method for generating descriptive trace gaps
A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and...
US-9,242,858 Instruction register delay select outputs to clock delay circuitry
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-9,241,405 Interposer with extruded feed-through vias
A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded...
US-9,240,900 Wireless router system
Conventional routers employ a wired backplane that employs "long reach" serializer/deserializer (SerDes) links, but this type of architecture is complicated,...
US-9,240,814 Ultrasonic receiver front-end
In certain embodiments, systems for receiving one or more echoes are provided. The system comprises a first attenuator, a first amplifier, and a second...
US-9,240,801 Analog-to-digital converter
A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop...
US-9,240,798 On-chip analog-to-digital converter (ADC) linearity text for embedded devices
A method for testing linearity of an ADC, comprising receiving a trigger signal indicating an ADC input voltage step adjustment, reading an ADC output sample...
US-9,240,767 Temperature-controlled integrated piezoelectric resonator apparatus
An integrated resonator apparatus comprises a piezoelectric resonator, an acoustic Bragg reflector coupled to the piezoelectric resonator, and a substrate on...
US-9,240,720 Emulation based ripple cancellation for a DC-DC converter
DC to DC converters and pulse width modulation controllers are presented with compensation circuitry to mitigate discontinuous conduction mode (DCM) undershoot...
US-9,240,619 Differential transmission line pairs using a coupling orthogonalization approach to reduce cross-talk
An apparatus is provided. The apparatus generally comprises a plurality of pairs of differential transmission lines. The plurality of pairs of differential...
US-9,240,465 Trench gate trench field plate semi-vertical semi-lateral MOSFET
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical...
US-9,240,446 Vertical trench MOSFET device in integrated power technologies
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift...
US-9,240,404 Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology...
US-9,240,400 Scheme to reduce stress of input/ output (IO) driver
An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot...
US-9,240,367 Semiconductor package with cantilever leads
A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive...
US-9,240,189 Real-time scheduling method with reduced input/output latency and improved tolerance for variable processing time
A method and apparatus for processing encoded audio data that operates on batches of data having a predetermined time block size. An input/output memory buffer...
US-9,239,798 Prefetcher with arbitrary downstream prefetch cancelation
A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter...
US-9,239,748 Comparator circuitry coupled to first, second time stamp overlap bits
This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined...
US-9,239,735 Compiler-control method for load speculation in a statically scheduled microprocessor
A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction...
US-9,239,368 Methods and apparatus for continuous ground fault self-test
Methods and apparatus for continuous ground fault self-test are disclosed. An example ground fault detection device includes a sense coil to detect current in a...
US-9,239,360 DFT approach to enable faster scan chain diagnosis
A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that...
US-9,239,353 Testing of integrated circuits with external clearance requirements
A method of testing an integrated circuit clearance distance device ("ICCDD") having a predetermined clearance distance in air requirement and a predetermined...
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