Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: texas instruments





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,240,798 On-chip analog-to-digital converter (ADC) linearity text for embedded devices
A method for testing linearity of an ADC, comprising receiving a trigger signal indicating an ADC input voltage step adjustment, reading an ADC output sample...
US-9,240,767 Temperature-controlled integrated piezoelectric resonator apparatus
An integrated resonator apparatus comprises a piezoelectric resonator, an acoustic Bragg reflector coupled to the piezoelectric resonator, and a substrate on...
US-9,240,720 Emulation based ripple cancellation for a DC-DC converter
DC to DC converters and pulse width modulation controllers are presented with compensation circuitry to mitigate discontinuous conduction mode (DCM) undershoot...
US-9,240,619 Differential transmission line pairs using a coupling orthogonalization approach to reduce cross-talk
An apparatus is provided. The apparatus generally comprises a plurality of pairs of differential transmission lines. The plurality of pairs of differential...
US-9,240,465 Trench gate trench field plate semi-vertical semi-lateral MOSFET
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical...
US-9,240,446 Vertical trench MOSFET device in integrated power technologies
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift...
US-9,240,404 Embedded polysilicon resistor in integrated circuits formed by a replacement gate process
An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (MOS) technology...
US-9,240,400 Scheme to reduce stress of input/ output (IO) driver
An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot...
US-9,240,367 Semiconductor package with cantilever leads
A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive...
US-9,240,189 Real-time scheduling method with reduced input/output latency and improved tolerance for variable processing time
A method and apparatus for processing encoded audio data that operates on batches of data having a predetermined time block size. An input/output memory buffer...
US-9,239,798 Prefetcher with arbitrary downstream prefetch cancelation
A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter...
US-9,239,748 Comparator circuitry coupled to first, second time stamp overlap bits
This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined...
US-9,239,735 Compiler-control method for load speculation in a statically scheduled microprocessor
A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction...
US-9,239,368 Methods and apparatus for continuous ground fault self-test
Methods and apparatus for continuous ground fault self-test are disclosed. An example ground fault detection device includes a sense coil to detect current in a...
US-9,239,360 DFT approach to enable faster scan chain diagnosis
A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that...
US-9,239,353 Testing of integrated circuits with external clearance requirements
A method of testing an integrated circuit clearance distance device ("ICCDD") having a predetermined clearance distance in air requirement and a predetermined...
US-9,238,870 Plasma etch for chromium alloys
A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at...
US-9,238,249 Ultrasound transmitter
A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the...
US-9,237,352 Methods and systems for encoding pictures associated with video data
Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing...
US-9,237,340 Camera pose estimation
A method of camera pose estimation is provided that includes capturing a model image of a scene at a canonical camera pose, generating an image library from...
US-9,236,902 Combined equalizer and spread spectrum interference canceller method and implementation for the downlink of...
The present invention describes a method and apparatus for implementing a mobile receiver (10) that combats multiple access interference (MAI) in a code...
US-9,236,809 Automatic timing adjustment for synchronous rectifier circuit
A circuit includes a conduction detector configured to monitor conduction of a body diode of a synchronous rectifier switch relative to a predetermined...
US-9,236,748 Method and apparatus of charging the battery with globally minimized integral degradation possible for...
An apparatus and method for charging a battery with an improved charging performance and a reduced degradation of the battery. A battery charging profile is...
US-9,236,113 Read assist for an SRAM using a word line suppression circuit
A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression...
US-9,236,107 FRAM cell with cross point access
A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns....
US-9,236,096 Initializing dummy bits of an SRAM tracking circuit
An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A...
US-9,235,310 Apparatus to detect dual gesture on a resistive screen
A resistive touch screen controller provides two-finger gesture recognition. Current mirror circuitry, coupled to the XP/XN and YP/YN conductors, generates a...
US-9,235,045 Phosphor wheel illumination using laser light reflective region
Image projection illumination apparatus and methods are provided. A color wheel has a blue laser light reflecting region and other regions respectively coated...
US-9,232,237 Block-based parallel deblocking filter in video coding
Deblocking filtering is provided in which an 8.times.8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering...
US-9,231,770 Combined digital certificate
A system can comprise a memory to store computer readable instructions and a processing unit to access the memory and to execute the computer readable...
US-9,231,732 Packet header protection for utility networks
A networking device includes a packet header protect generator, a transmitter, a receiver, a decoder and router. The transmitter transmits a data packet to the...
US-9,231,666 Enabling coordinated multi-point reception
This invention measures the propagation delay .tau..sub.1 between the user equipment and a first cooperating unit and the propagation delay .tau..sub.2 between...
US-9,231,658 Coexistence primitives in power line communication networks
Systems and methods for setting a Network Allocation Vector (NAV) in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes...
US-9,231,657 Adaptive sub-band algorithm for point-to-point communication in PLC networks
Embodiments of methods and systems for adaptive sub-band point-to-point communication are presented. In one embodiment a method includes performing functions...
US-9,231,648 Methods and apparatus for frequency offset estimation and correction prior to preamble detection of direct...
Methods and apparatus for frequency offset estimation and correction prior to preamble detection of DSSS signals. An integrated circuit is disclosed including a...
US-9,231,625 Low power, low out-of-band harmonic content radio
A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer...
US-9,231,476 Tracking energy consumption using a boost-buck technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,231,409 Sourcing and securing dual supply rails of tamper protected battery backed domain
This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and...
US-9,231,403 ESD protection circuit with plural avalanche diodes
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and...
US-9,231,054 Drain extended CMOS with counter-doped drain extension
An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS...
US-9,231,025 CMOS-based thermoelectric device with reduced electrical resistance
An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate...
US-9,230,887 Multiple depth vias in an integrated circuit
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with...
US-9,230,862 Wafer die separation
A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet...
US-9,230,852 Integrated circuit (IC) having electrically conductive corrosion protecting cap over bond pads
An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one...
US-9,230,851 Reduction of polysilicon residue in a trench for polysilicon trench filling processes
A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a...
US-9,230,732 Wireless power transfer
A wireless power transmitter can include a transmitting coil configured to wirelessly transmit power to a receiving coil. The wireless power transmitter can...
US-9,230,296 Spatial and temporal pulse width modulation method for image display
A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the...
US-9,229,066 Integrated fluxgate magnetic sensor and excitation circuitry
Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation...
US-9,229,058 Die attach pick error detection
Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during...
US-9,229,056 IC die top, bottom signals, tap lock, test, scan circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.