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Patent # Description
US-9,239,360 DFT approach to enable faster scan chain diagnosis
A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that...
US-9,239,353 Testing of integrated circuits with external clearance requirements
A method of testing an integrated circuit clearance distance device ("ICCDD") having a predetermined clearance distance in air requirement and a predetermined...
US-9,238,870 Plasma etch for chromium alloys
A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at...
US-9,238,249 Ultrasound transmitter
A circuit for driving ultrasound transducers uses a sample-and-hold circuit to sample multiple sample periods of a transducer driving waveform, and uses the...
US-9,237,352 Methods and systems for encoding pictures associated with video data
Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing...
US-9,237,340 Camera pose estimation
A method of camera pose estimation is provided that includes capturing a model image of a scene at a canonical camera pose, generating an image library from...
US-9,236,902 Combined equalizer and spread spectrum interference canceller method and implementation for the downlink of...
The present invention describes a method and apparatus for implementing a mobile receiver (10) that combats multiple access interference (MAI) in a code...
US-9,236,809 Automatic timing adjustment for synchronous rectifier circuit
A circuit includes a conduction detector configured to monitor conduction of a body diode of a synchronous rectifier switch relative to a predetermined...
US-9,236,748 Method and apparatus of charging the battery with globally minimized integral degradation possible for...
An apparatus and method for charging a battery with an improved charging performance and a reduced degradation of the battery. A battery charging profile is...
US-9,236,113 Read assist for an SRAM using a word line suppression circuit
A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression...
US-9,236,107 FRAM cell with cross point access
A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns....
US-9,236,096 Initializing dummy bits of an SRAM tracking circuit
An embodiment of the invention discloses a method for writing concurrently a binary logical value to one or more dummy memory cells in a dummy bit line pair. A...
US-9,235,310 Apparatus to detect dual gesture on a resistive screen
A resistive touch screen controller provides two-finger gesture recognition. Current mirror circuitry, coupled to the XP/XN and YP/YN conductors, generates a...
US-9,235,045 Phosphor wheel illumination using laser light reflective region
Image projection illumination apparatus and methods are provided. A color wheel has a blue laser light reflecting region and other regions respectively coated...
US-9,232,237 Block-based parallel deblocking filter in video coding
Deblocking filtering is provided in which an 8.times.8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering...
US-9,231,770 Combined digital certificate
A system can comprise a memory to store computer readable instructions and a processing unit to access the memory and to execute the computer readable...
US-9,231,732 Packet header protection for utility networks
A networking device includes a packet header protect generator, a transmitter, a receiver, a decoder and router. The transmitter transmits a data packet to the...
US-9,231,666 Enabling coordinated multi-point reception
This invention measures the propagation delay .tau..sub.1 between the user equipment and a first cooperating unit and the propagation delay .tau..sub.2 between...
US-9,231,658 Coexistence primitives in power line communication networks
Systems and methods for setting a Network Allocation Vector (NAV) in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes...
US-9,231,657 Adaptive sub-band algorithm for point-to-point communication in PLC networks
Embodiments of methods and systems for adaptive sub-band point-to-point communication are presented. In one embodiment a method includes performing functions...
US-9,231,648 Methods and apparatus for frequency offset estimation and correction prior to preamble detection of direct...
Methods and apparatus for frequency offset estimation and correction prior to preamble detection of DSSS signals. An integrated circuit is disclosed including a...
US-9,231,625 Low power, low out-of-band harmonic content radio
A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer...
US-9,231,476 Tracking energy consumption using a boost-buck technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,231,409 Sourcing and securing dual supply rails of tamper protected battery backed domain
This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and...
US-9,231,403 ESD protection circuit with plural avalanche diodes
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and...
US-9,231,054 Drain extended CMOS with counter-doped drain extension
An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS...
US-9,231,025 CMOS-based thermoelectric device with reduced electrical resistance
An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate...
US-9,230,887 Multiple depth vias in an integrated circuit
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with...
US-9,230,862 Wafer die separation
A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet...
US-9,230,852 Integrated circuit (IC) having electrically conductive corrosion protecting cap over bond pads
An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one...
US-9,230,851 Reduction of polysilicon residue in a trench for polysilicon trench filling processes
A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a...
US-9,230,732 Wireless power transfer
A wireless power transmitter can include a transmitting coil configured to wirelessly transmit power to a receiving coil. The wireless power transmitter can...
US-9,230,296 Spatial and temporal pulse width modulation method for image display
A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the...
US-9,229,066 Integrated fluxgate magnetic sensor and excitation circuitry
Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation...
US-9,229,058 Die attach pick error detection
Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during...
US-9,229,056 IC die top, bottom signals, tap lock, test, scan circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,229,055 Decompressed scan chain masking circuit shift register with log2(n/n) cells
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to...
US-9,227,836 Hermetic plastic molded MEMS device package and method of fabrication
A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110)...
US-9,219,526 Channel selection in power line communications
Systems for channel selection in power line communications (PLC) are described. In some embodiments, a PLC device may include a processor and a memory. The...
US-9,219,296 Coupler to launch electromagnetic signal from microstrip to dielectric waveguide
A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core...
US-9,219,052 Making a flip-chip assembly with bond fingers
A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally...
US-9,219,019 Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound
A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the...
US-9,218,981 Hydrogen passivation of integrated circuits
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping...
US-9,218,892 Error prediction in logic and memory devices
Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering...
US-9,218,504 Method and apparatus for secure mode indication
A method and apparatus for a hand-held device for ensuring a secured mode transition. The method includes receiving a request to transition to a mode,...
US-9,214,939 Adaptive bus termination apparatus and methods
Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor...
US-9,214,860 Comparator multiplexing LDO and converted output to DC-DC converter circuitry
A DC-DC converter receives input power from a power source and generates a regulated DC voltage as an output. The DC-DC converter contains multiple blocks, each...
US-9,214,440 Method for preventing die pad delamination
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a...
US-9,214,415 Integrating multi-output power converters having vertically stacked semiconductor chips
A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical...
US-9,214,269 IC rectangular inductor with perpendicular center and side shield traces
An inductive device is provided, which includes a substrate, a layer having a plurality of conductive metal traces and a metal shield layer. The conductive...
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