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Patent # Description
US-9,194,896 Tracking energy consumption using a sepic-converter technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,194,893 Bi-directional input, bi-directional output, lossless current sensing scheme with temperature compensation
A sensing circuit for a power FET. A first sensing FET senses current flow from load to ground. A second sensing FET senses current flow from ground to load....
US-9,194,707 Accelerometer-aided gyroscope
A method comprises computing a metric based on the accelerometer signal to remove an acceleration due to gravity. A bandwidth of a gyroscope filter is set based...
US-9,191,194 Data transfer clock recovery for legacy systems
The present invention provides method and apparatus for adapting a relatively high data rate second order serdes receiver to receive relatively low data rate...
US-9,191,160 Transmission of acknowledge/not-acknowledge with repetition
In ACK/NAK responses with repetition, the ACK/NAK response from the user equipment to a Physical Downlink Shared CHannel (PDSCH) transmission is repeated in...
US-9,191,088 Transmission modes and signaling for uplink MIMO support or single TB dual-layer transmission in LTE uplink
An apparatus for mapping data in a wireless communication system. The apparatus includes circuitry for generating a precoding matrix for multi-antenna...
US-9,190,982 RF mixer filter MEMS resonator array
A MEMS mixer filter including an array of a multiplicity of resonator elements with conductive outer surfaces in a coplanar rectangularly tiled array, and two...
US-9,190,462 Semiconductor device and method for low resistive thin film resistor interconnect
The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is...
US-9,190,341 Lidded integrated circuit package
A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded...
US-9,190,277 Combining ZTCR resistor with laser anneal for high performance PMOS transistor
An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with...
US-9,189,456 Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and...
The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic....
US-9,189,354 Pseudo dedicated debug port with an application interface
A method is shown to provide remote access to one or more debug access points whose functions include capabilities other than accessing memories across an...
US-9,189,331 Programmable address-based write-through cache control
This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a...
US-9,188,832 Method and system for generating a display
A method of displaying an image includes alternating an active state of each of a plurality of light sources. The light sources each generate a light beam when...
US-9,188,641 IC tap/scan selecting between TDI/SI and a test pattern source
An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a...
US-9,188,639 Linking circuitry for IC TAP, core TAP, off-chip TAP interface
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-9,185,421 System and method for video transcoding
A video transcoding system includes a video decoder, a video encoder, and a video interface. The video decoder is configured to decode a received video signal....
US-9,185,314 Mitigating the effects of signal overload in analog front-end circuits used in image sensing systems
Output voltage of a charge-to-voltage converter used in an image sensing system is compared with one or more thresholds to determine if the output voltage...
US-9,184,971 Apparatus for and method of robust packet detection and frequency offset estimation
A novel and useful apparatus for and method of packet detection and carrier frequency offset estimation. The packet detection mechanism is robust to channels...
US-9,184,967 System and method for generating frame structure for MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,184,794 Cyclic shift selection for MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,184,784 Method and apparatus for digital predistortion for a switched mode power amplifier
A method includes receiving an input signal and predistorting a baseband representation of the input signal at a carrier frequency and at one or more harmonic...
US-9,184,779 Dynamic medium switch in co-located PLC and RF networks
An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second...
US-9,184,762 Mismatch profile
A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC)...
US-9,184,761 Asynchronous to synchronous sampling using Akima algorithm
A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third...
US-9,184,226 Embedded tungsten resistor
A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR...
US-9,184,163 Low cost transistors
An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the...
US-9,184,121 Stacked synchronous buck converter having chip embedded in outside recess of leadframe
A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and...
US-9,184,120 Nonleaded package and leadframe strip and method
A nonleaded IC package, such as a QFN, including an encapsulation block having at least one generally flat lateral sidewall surface; and a plurality of leads,...
US-9,184,119 Lead frame with abutment surface
A lead frame device may include an integral die pad member, two separate finger members, a central body portion, each of the finger members have a top and a...
US-9,183,873 Laser diode driver damping circuit
A damping circuit having an input terminal and an output terminal is described. The damping circuit comprises a driver having an input and an output; an RC...
US-9,183,084 Memory attribute sharing between differing cache levels of multilevel cache
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the...
US-9,182,493 Fine time assistance for global navigation satellite systems
Apparatus and method for providing fine timing assistance to global navigation satellite systems (GNSS) via wireless local area network (WLAN). In one...
US-9,182,453 Hall sensor excitation system
A Hall plate excitation system provides reduced offset and temperature dependence. The Hall plate excitation system includes a current source, a switching...
US-9,182,248 Power line communication network and discovery process
An apparatus for a power line communication network includes a power line transmitter/receiver, a processor coupled to the power line transmitter/receiver, and...
US-9,179,492 Electronic device, method and system for half duplex data transmission
An electronic device and method for half duplex data transmission in a long range keyless entry and go system, and more specifically to an RFID transponder, a...
US-9,179,362 Systems and methods for networking coding using Reed-Solomon codes
A method for network coding includes encoding a plurality of message packets to produce a plurality of encoded packets. Each message packet and each encoded...
US-9,179,112 Methods for combining camera and projector functions in a single device
Described are handheld devices with combined image capture and image projection functions. One embodiment includes modulating and capturing a light beam along...
US-9,178,589 Dual layer beam forming in cellular networks
Single user and multiuser MIMO transmission in a cellular network may be performed by selecting by a base station (eNB) to transmit either one or two...
US-9,178,525 Mismatch corrector
A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective...
US-9,178,499 Low-power offset-stored latch
A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset...
US-9,178,434 Integrated primary startup bias and MOSFET driver
Some implementations are directed to a A DC-to-DC converter that includes a power transformer having a primary side and a secondary side and a plurality of...
US-9,178,424 Switched mode DCDC converter efficiency improvement by adaptive driver stage
In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second...
US-9,178,422 Resonance-based single inductor output-driven DC-DC converter and method
A resonance-based DC-DC converter for converting a DC input voltage to a first DC output voltage (V.sub.OUT1) on a output conductor (9) includes an inductor (L)...
US-9,178,038 Raised source/drain MOS transistor and method of forming the transistor with an implant spacer and an epitaxial...
A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the...
US-9,178,037 Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
US-9,177,945 Packaged semiconductor device having multilevel leadframes configured as modules
Fabricating a packaged semiconductor device provides first planar leadframe with first leads and pads having attached electronic components. The first leadframe...
US-9,177,806 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,177,802 High tilt angle plus twist drain extension implant for CHC lifetime improvement
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one...
US-9,177,546 Cloud based adaptive learning for distributed sensors
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sound parameter information is extracted from...
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