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Patent # Description
US-9,165,865 Ultra-thin power transistor and synchronous buck converter having customized footprint
A packaged power transistor device (100) having a leadframe including a flat plate (110) and a coplanar flat strip (120) spaced from the plate, the plate having...
US-9,164,528 Apparatus and method for controlling inductor current in a switch mode power supply
Apparatus and method for controlling inductor current in a switch mode power supply. In one embodiment, a switch mode power supply includes an inductor, a...
US-9,164,146 Tap and shadow access port output circuitry with clock doubler
The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform...
US-9,163,941 System and method for implementing low-cost electronic gyroscopes and accelerometer
Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter...
US-9,161,256 CQI feedback structure
Embodiments of the present disclosure provide a reporting allocation unit, an indicator interpretation unit and methods of operating a reporting allocation unit...
US-9,161,058 Method and system for detecting global brightness change for weighted prediction in video encoding
A method of encoding a coding unit of a digital video sequence is provided that includes computing a brightness measure for each region in a plurality of...
US-9,161,056 Method for low memory footprint compressed video decoding
This invention is a method of memory saving in compressed video decoding. For each group of pictures the method determines whether less than the maximum number...
US-9,160,996 Imaging input/output with shared spatial modulator
An image input/output apparatus and method includes a light source in optical communication with a spatial radiation modulator for projecting an output image...
US-9,160,410 Coexistence method by requesting access to the channel
Systems and methods for implementing coexistence by requesting access to a channel in power line communications (PLC) are described. In an illustrative...
US-9,160,358 Close-in tones
A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output...
US-9,160,330 Boost capacitor sharing architecture for power supply active balancing systems
An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a...
US-9,160,314 Negative edge flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable...
US-9,160,229 DC-DC converter
A DC-DC converter, having an output voltage and including at least one electronic switch; first circuitry controlling the output voltage by adjusting a...
US-9,159,725 Controlled on and off time scheme for monolithic cascoded power transistors
A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a...
US-9,159,603 Integrated circuit package strip support assembly
An integrated circuit ("IC") package strip support assembly for a saw table including a first material having a first hardness and having a surface adapted to...
US-9,159,276 Method for creating bit planes using a digital signal processor and double index addressing direct memory access
According to one embodiment of the present invention, a method for creating bit planes from frame data for a digital mirror device is disclosed including...
US-9,158,683 Multiport memory emulation using single-port memory devices
A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands...
US-9,157,958 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,157,938 On-time based peak current density rule and design method
A method of computing a peak current density specification (j.sub.peakspec) for an electrical conductor line of an integrated circuit (IC) resulting from...
US-9,157,897 High voltage ultrasound transmitter with gate protection diodes and intrinsic output zeroing
An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter...
US-9,157,807 Etching cavity structures in silicon under dielectric membrane
A semiconductor device includes a semiconductor layer (2) and a dielectric stack (3) on the semiconductor layer. A plurality of etchant openings (24-1,2 . . . )...
US-9,157,768 Inductive sensing including inductance multiplication with series connected coils
Inductive position sensing uses inductance multiplication with series connected sensor coils. In one embodiment, a first sensing domain area is established in a...
US-9,155,056 Mapping schemes for secondary synchronization signal scrambling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-9,154,801 Method and apparatus for diagonal scan and simplified coding of transform coefficients
A method and apparatus for encoding video data. At least a portion of a two dimensional array of transform coefficients representing a portion of video data is...
US-9,154,350 PHY layer options for body area network (BAN) devices
In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN)...
US-9,154,277 Resource allocation and signaling for aperiodic sounding
This patent application considers the configuration aperiodic sounding reference signal parameters by radio resource control signaling and the triggering of...
US-9,154,158 Macro-block encoding of skipped video frames
A video system includes an encoder for generating a compressed bit stream in response to a received video signal. A transitional location is located in the bit...
US-9,154,133 ESD robust level shifter
An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and...
US-9,153,726 Inductive optical sensor utilizing frontside processing of photo sensitive material
A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows...
US-9,153,569 Segmented NPN vertical bipolar transistor
A segmented bipolar transistor includes a p-base in a semiconductor surface including at least one p-base finger having a base metal/silicide stack including a...
US-9,153,295 Register bank cross path connection method in a multi core processor system
Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register...
US-9,153,228 Wireless telephone sending speech data in second packet secondary stage
An IC processor circuit has an interface for a microphone and a packet switched network. A memory holds bits for converting audible speech from the microphone...
US-9,152,875 Preserving text quality in video encoding
A video encoder receives a macro-block of an image frame, and determines whether the macro-block contains text. The video encoder computes a quantization...
US-9,152,586 Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a...
US-9,152,520 Programmable interface-based validation and debug
A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under...
US-9,151,842 Method and apparatus for time of flight sensor 2-dimensional and 3-dimensional map generation
A method and apparatus for Time Of Flight sensor 2-dimensional and 3-dimensional map generation. The method includes retrieving Time Of Flight sensor fixed...
US-9,150,410 Coatings for relatively movable surfaces
A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating...
US-9,148,699 Optimized algorithm for construction of composite video from a set of discrete video sources
A method includes reading a composite video descriptor data structure and a plurality of window descriptor data structures. The composite video descriptor data...
US-9,148,580 Transforming wide dynamic range images to reduced dynamic range images
A method of transforming an N-bit raw wide dynamic range (WDR) Bayer image to a K-bit raw red-green-blue (RGB) image wherein N>K is provided that includes...
US-9,148,316 Decision feedback equalizer
A decision feedback equalizer (DFE) circuit includes a first equalization path and a second equalization path. Each equalization path includes a summing node, a...
US-9,148,181 Reference clock compensation in DVB-H receivers
A wireless receiver providing multiple services (FIG. 3) is disclosed. The wireless receiver includes an oscillator circuit (304, FIG. 4) arranged to produce a...
US-9,148,166 Adding predefined offset to coarse ADC residue output to SAR
A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes...
US-9,148,159 Dual comparator-based error correction scheme for analog-to-digital converters
An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is...
US-9,147,764 Flatband shift for improved transistor performance
An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a...
US-9,147,756 Electronic device and method for increasing reliability of bipolar transistors under high voltage conditions
The invention relates to an electronic device with a bipolar transistor having an emitter, a base and a collector. The base has a first region of a first...
US-9,147,193 Method for transmission of unicast control in broadcast/multicast transmission time intervals
Embodiments of the invention provide methods for maximizing the bandwidth utilization in the uplink of a communication system supporting time division...
US-9,147,013 Wireless sensor with FRAM
A wireless sensor module for use in a wireless sensor network. The sensor module collects sensor data in a periodic manner with a first time period. The sensor...
US-9,146,825 At speed TAP, dual port router, and command flip-flop circuitry
This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift &...
US-9,146,600 Array and peripheral power control decoded from circuitry and registers
Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that...
US-9,146,570 Load current compesating output buffer feedback, pass, and sense circuits
A load current compensating output buffer circuit and method are disclosed. The circuit includes a buffer amplifier coupled to a supply voltage and the...
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