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Patent # Description
US-9,140,754 Scan-based MCM interconnecting testing
A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first...
US-9,140,751 Testing integrated circuit packaging for output short circuit current
An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously...
US-9,140,590 System and method of power-saving in MEMS sensor applications
At least some of the embodiments are methods including detecting low user dynamics by a first MEMS sensor, determining a first sensor sampling rate value...
US-9,140,413 Light emitting diode light bulb and incandescent lamp conversion apparatus
Apparatus and methods separate the functions of light emission, heat dissipation, and power conversion in LED lighting. Doing so may facilitate cost-effective...
US-9,137,862 Slew rate controlled transistor driver
A gate driver circuit providing a slew-rate controlled gate control signal while minimizing the stretching of the gate control signal relative to the input...
US-9,137,611 Method, system and computer program product for estimating a level of noise
In response to a signal failing to exceed an estimated level of noise by more than a predetermined amount for more than a predetermined continuous duration, the...
US-9,137,061 Method and circuit for transmitting data
Methods and circuits for transmitting data are disclosed. An embodiment of a method includes transmitting a predetermined number of pulses during predetermined...
US-9,136,908 Long preamble and duty cycle based coexistence mechanism for power line communication (PLC) networks
Embodiments of methods and systems for supporting coexistence of multiple technologies in a Power Line Communication (PLC) network are disclosed. A long...
US-9,136,899 Built in self test and method for RF transceiver systems
Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier...
US-9,136,887 Subtracting linear impairments for non-linear impairment digital pre-distortion error signal
Example embodiment of the systems and methods of linear impairment modeling to improve digital pre-distortion adaptation performance includes a DPD module that...
US-9,136,856 Background DAC calibration for pipeline ADC
A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A...
US-9,136,829 Method and apparatus for implementing a programmable high resolution ramp signal in digitally controlled power...
A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current...
US-9,136,813 Wireless network receiver
A wireless network receiver includes a detection module that uses preamble data in a data frame for signal processing functions and the detection module is...
US-9,136,796 Negative audio signal voltage protection circuit and method for audio ground circuits
Self-grounded circuitry (10) includes a signal channel conducting an output voltage (V.sub.OUT1). A charge pump (2) powered by a reference voltage (V.sub.DD)...
US-9,136,787 Back EMF monitor for motor control
An integrated circuit includes a motor current input voltage-to-current (VI) converter that receives a motor current sensor voltage from a motor and a reference...
US-9,136,724 Method for limiting battery discharging current in battery charger and discharger circuit
A power supply system includes a rechargeable battery to deliver a supply current to a load and a circuit to limit a discharge current when the rechargeable...
US-9,136,698 Power supply selector and method for minimizing an inrush current in a power supply selector
A method for minimizing an inrush current in a power supply selector and a power supply selector system is provided. The power supply selector includes a...
US-9,136,381 Super junction MOSFET with integrated channel diode
Semiconductor device includes MOSFET having planar cells on an epitaxial semiconductor surface of a first type providing a drain drift region. A first and...
US-9,136,368 Trench gate trench field plate semi-vertical semi-lateral MOSFET
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical...
US-9,136,256 Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips
Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer...
US-9,134,376 TDO multiplexers series coupling augmentation instruction register with instruction registers
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-9,134,372 IC linking module gating inputs of TAP select and enable
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-9,134,371 Translating operate state into operate scan paths, A, B, C
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
US-9,134,369 Tap, data input, output circuitry coupled to mode select lead
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-9,134,114 Time of flight sensor binning
A time-of-flight sensor device generates and analyzes a high-resolution depth map frame from a high-resolution image to determine a mode of operation for the...
US-9,131,518 Systems and methods for time optimization for silencing wireless devices in coexistence networks
Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid...
US-9,131,234 Signaling signed band offset values for sample adaptive offset (SAO) filtering in video coding
A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band...
US-9,131,210 Low-complexity two-dimensional (2D) separable transform design with transpose buffer management
Methods are provided for reducing the size of a transpose buffer used for computation of a two-dimensional (2D) separable transform. Scaling factors and clip...
US-9,130,904 Externally and internally accessing local NAS data through NSFV3 and 4 interfaces
A method for secure external access to a collaborative design system is provided that includes establishing a virtual private network (VPN) tunnel between an...
US-9,130,876 Producing silence packets in local buffer without sequencing, queuing, decoding
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing...
US-9,130,792 Closed-loop high-speed channel equalizer adaptation
A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an...
US-9,130,683 Silence based attenuation for enhanced idle-channel FM or other receiver co-existence with a coexisting radio...
An electronic circuit (100) for use in a wireless receiver (1720). The circuit (100) includes an audio demodulator (15), an audio envelope portion (35) operable...
US-9,130,636 Low power, low out-of-band harmonic content radio
A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer...
US-9,130,560 Edge rate control gate drive circuit and system for low side devices with driver FET
An apparatus, comprising a load; an output FET having a drain coupled to the load; a first and second of a pair strong FETs, wherein: a) a source of the first...
US-9,130,552 Cross-conduction detector for switching regulator
An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch...
US-9,130,377 System and method for battery pack management using predictive balancing
Predictive battery pack cell balancing apparatus and methods are presented in which active bypass current switching is controlled according to initial balancing...
US-9,129,955 Semiconductor flip-chip system having oblong connectors and reduced trace pitches
A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length...
US-9,129,886 Integrated piezoelectric resonator and additional active circuit
A semiconductor device comprises a semiconductor wafer; a piezoelectric resonator formed on the wafer, and an active circuit also formed on the wafer. The...
US-9,129,796 Pre-metal deposition clean process
A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation...
US-9,129,344 Method and system for padding in a video processing system
A method and system for padding an array of data on-the-fly in a direct memory access (DMA) controller. The method includes receiving the array of data in the...
US-9,129,071 Coherence controller slot architecture allowing zero latency write commit
This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this...
US-9,128,690 Bus pin reduction and power management
A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit...
US-9,128,571 Capacitive touch panel having improved response characteristics
An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection...
US-9,128,503 Unified bandgap voltage curvature correction circuit
A unified bandgap voltage waveform compensation amplifier is arranged having shared input transistor pairs, a shared load resistor, and shared current sources....
US-9,128,499 Apparatus and methods to control peak current mode controlled power converters using selective noise blanking
An apparatus and a method to control peak current mode controlled power converter system using selective noise blanking are disclosed. The control of the peak...
US-9,128,498 Dead-time compensation in a power supply system
A power supply system (10) includes a pulse-width modulation (PWM) system (14) configured to generate a PWM signal. The system (10) also includes a power stage...
US-9,128,152 Interface circuitry with JTAG interface, full and reduced pin interfaces
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-9,128,149 IC scan and test circuitry with up control circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,128,023 Calibration scheme for gas absorption spectra detection
A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission...
US-9,124,532 Multiple rank CQI feedback for cellular networks
Single user and multiuser MIMO transmission in a cellular network may be performed by a base station (eNB) transmitting either one, two, or more transmission...
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