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Cross-conduction detector for switching regulator
An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch...
System and method for battery pack management using predictive balancing
Predictive battery pack cell balancing apparatus and methods are presented in which active bypass current switching is controlled according to initial balancing...
Semiconductor flip-chip system having oblong connectors and reduced trace
A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length...
Integrated piezoelectric resonator and additional active circuit
A semiconductor device comprises a semiconductor wafer; a piezoelectric resonator formed on the wafer, and an active circuit also formed on the wafer. The...
Pre-metal deposition clean process
A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation...
Method and system for padding in a video processing system
A method and system for padding an array of data on-the-fly in a direct memory access (DMA) controller. The method includes receiving the array of data in the...
Coherence controller slot architecture allowing zero latency write commit
This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this...
Bus pin reduction and power management
A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit...
Capacitive touch panel having improved response characteristics
An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection...
Unified bandgap voltage curvature correction circuit
A unified bandgap voltage waveform compensation amplifier is arranged having shared input transistor pairs, a shared load resistor, and shared current sources....
Apparatus and methods to control peak current mode controlled power
converters using selective noise blanking
An apparatus and a method to control peak current mode controlled power converter system using selective noise blanking are disclosed. The control of the peak...
Dead-time compensation in a power supply system
A power supply system (10) includes a pulse-width modulation (PWM) system (14) configured to generate a PWM signal. The system (10) also includes a power stage...
Interface circuitry with JTAG interface, full and reduced pin interfaces
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
IC scan and test circuitry with up control circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
Calibration scheme for gas absorption spectra detection
A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission...
Multiple rank CQI feedback for cellular networks
Single user and multiuser MIMO transmission in a cellular network may be performed by a base station (eNB) transmitting either one, two, or more transmission...
Communication device with sleep state indicator and state machine control
A device with an autonomous sleep characteristic, which is in communication with a host, is described. The device includes one or more communication subsystems....
Flexible PRBS architecture for a transceiver
An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled...
Mitigation of interference between wireless networks
A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating...
Dual loop digital predistortion for power amplifiers
A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of...
Body bias coordinator, method of coordinating a body bias and sub-circuit
power supply employing the same
A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit...
Systems and methods of smooth light load operation in a DC/DC converter
Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction...
Vertical trench MOSFET device in integrated power technologies
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift...
Chip to dielectric waveguide interface for sub-millimeter wave
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
Integrated passive flip chip package
A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the...
Integration scheme for changing crystal orientation in hybrid orientation
technology (HOT) using direct silicon...
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such...
Layout method to minimize context effects and die area
An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region...
Self clocking for data extraction
A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is...
Electrophoretic display with software recognizing first and second
Electrophoretic displays (EPDs) and methods for controlling EPDs are disclosed herein. An embodiment of an EPD includes a first operating format, wherein pixels...
Caching method and system for video coding
A method of caching reference data in a reference data cache is provided that includes receiving an address of a reference data block in the reference data...
Detecting wave gestures near an illuminated surface
A method for wave gesture detection performed by a touch processor in an optical touch detection system is provided. The method includes receiving a sequence of...
Semiconductor test system and method
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
TAP with commandable data register control router and routing circuit
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
Tap linking module test access port controller with enable input
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these...
Parallel scan path distributor/collector controller having serial and
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these...
System clock counter counting ring oscillator pulses during programmed
A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator....
Attitude estimation for pedestrian navigation using low cost MEMS
accelerometer in mobile applications, and...
A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor...
Method of forming a laminated magnetic core with sputter deposited and
A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between...
Assembly method for converting the precursors to capacitors
A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor and an integrated circuit on a surface of a substrate....
Low power excess loop delay compensation technique for delta-sigma
A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog...
Scheme to improve the performance and reliability in high voltage IO
circuits designed using low voltage devices
A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO...
Phase-shifted dual-bridge DC/DC converter with wide-range ZVS and zero
Disclosed is a family of new DC/DC converters and a new control method. The converter comprises two bridge inverters, two full-wave rectification circuits and a...
Power supply control method for constant current constant power control
A digital power supply and power supply controller are presented, including a voltage control loop and a current control loop, with a controller for pulse width...
Alignment to multiple layers
A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a...
Low cost transistors
An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the...
High voltage CMOS with triple gate oxide
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a...
Single sided bit line restore for power reduction
A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array....
Use of three-dimensional top-down views for business analytics
A method of analyzing a depth image in a digital system is provided that includes detecting a foreground object in a depth image, wherein the depth image is a...
Method to extend data retention for flash based storage in a real time
device processed on generic...
This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention...
ASIP with reconfigurable circuitry implementing atomic operations of a PLL
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...