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Patent # Description
US-9,231,648 Methods and apparatus for frequency offset estimation and correction prior to preamble detection of direct...
Methods and apparatus for frequency offset estimation and correction prior to preamble detection of DSSS signals. An integrated circuit is disclosed including a...
US-9,231,625 Low power, low out-of-band harmonic content radio
A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer...
US-9,231,476 Tracking energy consumption using a boost-buck technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,231,409 Sourcing and securing dual supply rails of tamper protected battery backed domain
This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and...
US-9,231,403 ESD protection circuit with plural avalanche diodes
An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and...
US-9,231,054 Drain extended CMOS with counter-doped drain extension
An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS...
US-9,231,025 CMOS-based thermoelectric device with reduced electrical resistance
An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate...
US-9,230,887 Multiple depth vias in an integrated circuit
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with...
US-9,230,862 Wafer die separation
A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet...
US-9,230,852 Integrated circuit (IC) having electrically conductive corrosion protecting cap over bond pads
An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one...
US-9,230,851 Reduction of polysilicon residue in a trench for polysilicon trench filling processes
A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a...
US-9,230,732 Wireless power transfer
A wireless power transmitter can include a transmitting coil configured to wirelessly transmit power to a receiving coil. The wireless power transmitter can...
US-9,230,296 Spatial and temporal pulse width modulation method for image display
A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the...
US-9,229,066 Integrated fluxgate magnetic sensor and excitation circuitry
Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation...
US-9,229,058 Die attach pick error detection
Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during...
US-9,229,056 IC die top, bottom signals, tap lock, test, scan circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,229,055 Decompressed scan chain masking circuit shift register with log2(n/n) cells
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to...
US-9,227,836 Hermetic plastic molded MEMS device package and method of fabrication
A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110)...
US-9,219,526 Channel selection in power line communications
Systems for channel selection in power line communications (PLC) are described. In some embodiments, a PLC device may include a processor and a memory. The...
US-9,219,296 Coupler to launch electromagnetic signal from microstrip to dielectric waveguide
A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core...
US-9,219,052 Making a flip-chip assembly with bond fingers
A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally...
US-9,219,019 Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound
A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the...
US-9,218,981 Hydrogen passivation of integrated circuits
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping...
US-9,218,892 Error prediction in logic and memory devices
Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering...
US-9,218,504 Method and apparatus for secure mode indication
A method and apparatus for a hand-held device for ensuring a secured mode transition. The method includes receiving a request to transition to a mode,...
US-9,214,939 Adaptive bus termination apparatus and methods
Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor...
US-9,214,860 Comparator multiplexing LDO and converted output to DC-DC converter circuitry
A DC-DC converter receives input power from a power source and generates a regulated DC voltage as an output. The DC-DC converter contains multiple blocks, each...
US-9,214,440 Method for preventing die pad delamination
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a...
US-9,214,415 Integrating multi-output power converters having vertically stacked semiconductor chips
A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical...
US-9,214,269 IC rectangular inductor with perpendicular center and side shield traces
An inductive device is provided, which includes a substrate, a layer having a plurality of conductive metal traces and a metal shield layer. The conductive...
US-9,213,656 Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
US-9,213,316 Circuit for detecting and correcting timing errors
A circuit for detecting and correcting timing errors. A timing circuit includes an interpolator. The interpolator includes a fine counter, a coarse counter, and...
US-9,213,062 Addressable tap address, state monitor, decode and TMS gating circuitry
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
US-9,213,061 Operating state machine from reset to poll in to reset
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-9,213,048 System and method for testing an electronic device
Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip...
US-9,210,748 Systems and methods of driving multiple outputs
Systems and methods of driving multiple outputs are provided in which a single inductor may be used to drive multiple output such as independent strings of LEDs...
US-9,210,008 SerDes communications with retiming receiver supporting link training
A SerDes corn link with a retiming receiver is operable in link training (LT) mode. A SerDes transmitter includes a TX FIR channel driver to transmit TX Data...
US-9,209,842 Method and circuitry for transmitting data
Data transfer devices and methods for transferring data between first and second circuits are disclosed. A data transfer device includes a first circuit having...
US-9,209,791 Circuits and methods for cancelling nonlinear distortions in pulse width modulated sequences
A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input...
US-9,209,761 Combined input stage for transconductance amplifier having gain linearity over increased input voltage range
First and second transconductance amplifier input stages having first and second gain characteristics, respectively, are combined. The resulting combined input...
US-9,209,700 Magnetic sensing technique for power supply systems
One embodiment includes a power supply system including a transformer comprising a primary, secondary, and auxiliary winding that are magnetically coupled. The...
US-9,209,632 Systems and methods of direct cell attachment for batteries
Embodiments of the systems and methods of direct cell attachment for battery cells disclosed herein operate without the protection FETs and the protection IC,...
US-9,209,195 SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array
An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as...
US-9,208,902 Bitline leakage detection in memories
An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay...
US-9,208,899 Universal test structures based SRAM on-chip parametric test module and methods of operating and testing
An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and...
US-9,208,893 Read margin measurement in a read-only memory
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of...
US-9,208,545 Adaptive weighted-local-difference order statistics filters
A novel modification to the order statistics filters called the Adaptive Weighted-Local-Difference Order Statistics is shown that will act as a generic...
US-9,208,120 Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and...
This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous...
US-9,207,280 First/second die, channel interfaces, TAPs, and TLMs with common clock
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-9,207,278 Testing integrated circuit packaging for shorts
An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more...
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