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Scan chain in an integrated circuit
In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where...
State machine shifting between idle, capture, shift 1, shift 2
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
Wireless system with hybrid automatic retransmission request in
A wireless receiver for receiving signals from an interference-limited transmitter in an interference-limited system comprising at least one transmit antenna,...
Carrier sense multiple access (CSMA) protocols for power line
Systems and methods for carrier sense multiple access (CSMA) protocols for power line communications (PLC) are described. In some embodiments, a method may...
First and second phase detectors and phase offset adder PLL
A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control...
Channel quality report processes, circuits and systems
An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a...
ACKNAK and CQI channel mapping schemes in wireless networks
A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to...
Measuring current in a power regulator system
One embodiment includes a power regulator system. The system includes a gate driver circuit configured to generate switching signal and a switching circuit...
Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask
films for improved EPI profile
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon...
Dielectric liner added after contact etch before silicide formation
A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon,...
Determining optimum code from default, programmable, and test trim codes
In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting...
CMOS process to improve SRAM yield
An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall...
Spacer shaper formation with conformal dielectric film for void free PMD
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
Driver for normally on III-nitride transistors to get normally-off
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
Systems and methods for software instruction translation from a high-level
language to a specialized...
A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when...
Microprocessor unit capable of multiple power modes having a register with
direct control bits and register...
A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The...
Systems and methods of battery cell anomaly detection
Systems and methods for cell anomaly detection are provided. The disclosed systems and methods of cell anomaly detection may use a single circuit to detect both...
Scan chain masking qualification circuit shift register and bit-field
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to...
Scan test controller with state machine and gates
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
Controlling an epitaxial growth process in an epitaxial reactor
A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as...
WiFi establishing a protected medium duration for USB-like wireless
A master electronic circuit includes a storage representing a wireless collision avoidance networking process involving collision avoidance overhead and...
Transceiver with asymmetric matching network
A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable...
Downlink 8 TX codebook sub-sampling for CSI feedback
This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook...
Dual-port positive level sensitive data retention latch
In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked...
Resonant impedance sensing based on controlled negative impedance
Resonant impedance sensing with a resonant sensor (such as LC) is based on generating a controlled negative impedance to maintain steady-state oscillation in...
Buck-boost converter with buck-boost transition switching control
A buck-boost regulation methodology operable, in one embodiment, with a single inductor, four-switch (S1-S4) buck-boost regulator configured for DCM. Buck-boost...
Adjusting voltage regulator operating parameters
Within an electronic device, a voltage regulator powers a load. The voltage regulator has adjustable operating parameters that can be set during operation of...
Reverse voltage condition protection in a power supply system
One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an...
Structure and method for metal gate stack oxygen concentration control
using an oxygen diffusion barrier layer...
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the...
Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
Clam shell two-pin wafer holder for metal plating
A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the...
Use of dielectric slots for reducing via resistance in dual damascene
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The...
IC with floating buried layer ring for isolation of embedded islands
An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of...
Wireless power system and method
A wireless power system and method are provided that employ a hybrid approach to adjusting transmission power to take advantages of the best features of...
TCAM with efficient multiple dimension range search capability
An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the...
TCAM with efficient range search capability
An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data...
Virtual register mode by designation of dedicated register as destination
operand with switch connecting...
The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback...
Circuits and methods for reducing flicker in an LED light source
Method and circuits for balancing a first waveform used to drive an LED are disclosed herein. The first waveform has a first cycle with a first amplitude and a...
Digital phase angle detection and processing
Apparatus and methods operate to perform digital time sampling of a waveform associated with a rectified alternating current, edge-controlled power signal,...
On transparency of CoMP
This invention is a technique for coordinate multi-point wireless transmission between plural base stations and user equipment. At least one base station...
Adaptive coding structure and adaptive FCode determination in video coding
A method of encoding a digital video sequence is provided that includes computing a motion vector (MV) histogram and a motion threshold for a first frame of the...
Detecting double talk in acoustic echo cancellation using zero-crossing
A method for acoustic echo cancellation in a communication device is provided that includes receiving a first near-end audio signal in the communication device,...
Inserting source, sequence numbers into data stream from separate sources
A method of detecting lost data within a data stream by inserting sequence numbers within the stream. Network data blocks to be transmitted are assembled from...
Symbol-wise channel tracking for smart utility networks (SUN) orthogonal
frequency division multiplexing (OFDM)
A device for updating complex channel gain estimates for orthogonal frequency division multiplexed (OFDM) symbols that includes a receiver to receive a...
Positive edge flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a first inverter, a pass gate, master latch, a transfer gate and a slave latch. The clock...
Primary-side regulation for isolated power supplies
A DC-DC converter includes a primary side sense circuit to detect a load current of the DC-DC converter based on reflected current from a secondary winding of...
Input offset control
Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a...
First coupling transformer secondary winding coupling second transmitter
A device includes multiple transceivers, a coupling block and an antenna. The transceivers operate according to time-division multiple access (TDMA) techniques....
Photodiode employing surface grating to enhance sensitivity
A semiconductor device contains a photodiode formed in a substrate of the semiconductor device. At a top surface of the substrate, over the photodiode, a...