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Patent # Description
US-9,136,368 Trench gate trench field plate semi-vertical semi-lateral MOSFET
A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical...
US-9,136,256 Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips
Power supply system (100) comprises vertically sequentially a QFN leadframe (101), a first chip (110) with FET terminals on opposite sides, a flat interposer...
US-9,134,376 TDO multiplexers series coupling augmentation instruction register with instruction registers
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-9,134,372 IC linking module gating inputs of TAP select and enable
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-9,134,371 Translating operate state into operate scan paths, A, B, C
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan...
US-9,134,369 Tap, data input, output circuitry coupled to mode select lead
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-9,134,114 Time of flight sensor binning
A time-of-flight sensor device generates and analyzes a high-resolution depth map frame from a high-resolution image to determine a mode of operation for the...
US-9,131,518 Systems and methods for time optimization for silencing wireless devices in coexistence networks
Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid...
US-9,131,234 Signaling signed band offset values for sample adaptive offset (SAO) filtering in video coding
A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band...
US-9,131,210 Low-complexity two-dimensional (2D) separable transform design with transpose buffer management
Methods are provided for reducing the size of a transpose buffer used for computation of a two-dimensional (2D) separable transform. Scaling factors and clip...
US-9,130,904 Externally and internally accessing local NAS data through NSFV3 and 4 interfaces
A method for secure external access to a collaborative design system is provided that includes establishing a virtual private network (VPN) tunnel between an...
US-9,130,876 Producing silence packets in local buffer without sequencing, queuing, decoding
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing...
US-9,130,792 Closed-loop high-speed channel equalizer adaptation
A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an...
US-9,130,683 Silence based attenuation for enhanced idle-channel FM or other receiver co-existence with a coexisting radio...
An electronic circuit (100) for use in a wireless receiver (1720). The circuit (100) includes an audio demodulator (15), an audio envelope portion (35) operable...
US-9,130,636 Low power, low out-of-band harmonic content radio
A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer...
US-9,130,560 Edge rate control gate drive circuit and system for low side devices with driver FET
An apparatus, comprising a load; an output FET having a drain coupled to the load; a first and second of a pair strong FETs, wherein: a) a source of the first...
US-9,130,552 Cross-conduction detector for switching regulator
An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch...
US-9,130,377 System and method for battery pack management using predictive balancing
Predictive battery pack cell balancing apparatus and methods are presented in which active bypass current switching is controlled according to initial balancing...
US-9,129,955 Semiconductor flip-chip system having oblong connectors and reduced trace pitches
A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length...
US-9,129,886 Integrated piezoelectric resonator and additional active circuit
A semiconductor device comprises a semiconductor wafer; a piezoelectric resonator formed on the wafer, and an active circuit also formed on the wafer. The...
US-9,129,796 Pre-metal deposition clean process
A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation...
US-9,129,344 Method and system for padding in a video processing system
A method and system for padding an array of data on-the-fly in a direct memory access (DMA) controller. The method includes receiving the array of data in the...
US-9,129,071 Coherence controller slot architecture allowing zero latency write commit
This invention speeds operation for coherence writes to shared memory. This invention immediately commits to the memory endpoint coherence write data. Thus this...
US-9,128,690 Bus pin reduction and power management
A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit...
US-9,128,571 Capacitive touch panel having improved response characteristics
An apparatus is provided. The apparatus comprises a second layer disposed over a first layer. Each of the first and second layers have a set of detection...
US-9,128,503 Unified bandgap voltage curvature correction circuit
A unified bandgap voltage waveform compensation amplifier is arranged having shared input transistor pairs, a shared load resistor, and shared current sources....
US-9,128,499 Apparatus and methods to control peak current mode controlled power converters using selective noise blanking
An apparatus and a method to control peak current mode controlled power converter system using selective noise blanking are disclosed. The control of the peak...
US-9,128,498 Dead-time compensation in a power supply system
A power supply system (10) includes a pulse-width modulation (PWM) system (14) configured to generate a PWM signal. The system (10) also includes a power stage...
US-9,128,152 Interface circuitry with JTAG interface, full and reduced pin interfaces
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
US-9,128,149 IC scan and test circuitry with up control circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,128,023 Calibration scheme for gas absorption spectra detection
A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission...
US-9,124,532 Multiple rank CQI feedback for cellular networks
Single user and multiuser MIMO transmission in a cellular network may be performed by a base station (eNB) transmitting either one, two, or more transmission...
US-9,124,463 Communication device with sleep state indicator and state machine control
A device with an autonomous sleep characteristic, which is in communication with a host, is described. The device includes one or more communication subsystems....
US-9,124,462 Flexible PRBS architecture for a transceiver
An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled...
US-9,124,359 Mitigation of interference between wireless networks
A system and method for minimizing or preventing interference between wireless networks is disclosed. A network hub broadcasts a beacon signal within repeating...
US-9,124,324 Dual loop digital predistortion for power amplifiers
A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of...
US-9,124,263 Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same
A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit...
US-9,124,177 Systems and methods of smooth light load operation in a DC/DC converter
Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction...
US-9,123,802 Vertical trench MOSFET device in integrated power technologies
A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift...
US-9,123,737 Chip to dielectric waveguide interface for sub-millimeter wave communications link
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
US-9,123,626 Integrated passive flip chip package
A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the...
US-9,123,570 Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon...
Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such...
US-9,123,562 Layout method to minimize context effects and die area
An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region...
US-9,123,404 Self clocking for data extraction
A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is...
US-9,123,300 Electrophoretic display with software recognizing first and second operating formats
Electrophoretic displays (EPDs) and methods for controlling EPDs are disclosed herein. An embodiment of an EPD includes a first operating format, wherein pixels...
US-9,122,609 Caching method and system for video coding
A method of caching reference data in a reference data cache is provided that includes receiving an address of a reference data block in the reference data...
US-9,122,354 Detecting wave gestures near an illuminated surface
A method for wave gesture detection performed by a touch processor in an optical touch detection system is provided. The method includes receiving a sequence of...
US-9,121,906 Semiconductor test system and method
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-9,121,905 TAP with commandable data register control router and routing circuit
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
US-9,121,904 Tap linking module test access port controller with enable input
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these...
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