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Patent # Description
US-1,003,8577 Equalizer boost setting
One example includes a system that is comprised of an equalizer, a counter, and a controller. The equalizer equalizes an incoming signal and provide an...
US-1,003,8453 Capacitor calibration
An analog-to-digital converter includes a comparator, a capacitive digital-to-analog converter (DAC), and calibration circuitry. The capacitive DAC is coupled...
US-1,003,8436 Masking vd to vref after miller plateau and gate charge
A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS...
US-1,003,8403 Digital isolator
Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an...
US-1,003,8377 Precharging a capacitor with an offset to mitigate control delays in a buck converter
One example includes a power supply system. The system includes a power stage comprising at least one power switch that is periodically activated during an...
US-1,003,7814 Track and hold with active charge cancellation
A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor...
US-1,003,7439 Secure master and secure guest endpoint security firewall
This invention is a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure...
US-1,003,7287 Method for protecting memory against unauthorized access
A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access...
US-1,003,7071 Compute through power loss approach for processing device having nonvolatile logic memory
A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to...
US-1,003,6777 Selectively uncoupling tap and coupling OCI responsive to link instruction
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-1,003,6776 TMS pin for mode signal and output for read data
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-1,003,6656 Position detecting system based on inductive sensing
A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the...
US-1,003,4252 Short and long training fields
A method includes receiving a first plurality of symbols comprising complex portions. The method further includes applying conjugate symmetry to the first...
US-1,003,4022 Method and system for constraining slice header processing overhead in video coding
A method for encoding a picture of a video sequence in a bit stream that constrains slice header processing overhead is provided. The method includes computing...
US-1,003,3626 Conditional instructions for packet processing
A network switch includes a plurality of ports, a parser coupled to the plurality of ports, and a processor coupled to the ports and configured to process a...
US-1,003,3447 Downlink multiple input multiple output enhancements for single-cell with remote radio heads
A base station selects a subset of at least one geographically separated antennas for each of the plurality of user equipments. The base station forms at least...
US-1,003,3440 Inductive structures with reduced emissions and interference
In described examples, an inductive structure includes a power coil and a data coil. The data coil is substantially centered within the power coil. A first...
US-1,003,3427 Transmitter local oscillator leakage suppression
A system for reducing a local oscillator leakage component. The system includes a transmitter channel to transmit data modulated using a transmitter local...
US-1,003,3365 Digital clock-duty-cycle correction
A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The...
US-1,003,3342 Nonlinear class AB input stage
A circuit includes a differential input stage amplifier that receives a differential input voltage and generates an output voltage based on a difference in the...
US-1,003,3341 Programmable impedance network in an amplifier
The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A...
US-1,003,3331 Op-amp IC chip
An integrated circuit (IC) chip can include an operational amplifier with adjustable operational parameters. The IC chip can also include a trimming module...
US-1,003,3281 Integrated circuit with configurable control and power switches
Disclosed examples include integrated circuits configurable according to sensed circuit conditions to provide configurable power converter topologies with...
US-1,003,3276 Current sensing using capacitor voltage ripple in hybrid capacitor/inductor power converters
A DC-to-DC power converter includes a power stage, an output stage and a ripple magnitude detector. The power stage includes a plurality of transistors, an...
US-1,003,3271 Multi-stage charge pump
In described examples, a multi-stage charge pump includes first, second and third charge pump stages connected in series. Each of the first, second and third...
US-1,003,2868 High performance super-beta NPN (SBNPN)
A method for making a super .beta. NPN (SBNPN) transistor includes depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer; depositing a...
US-1,003,2850 Semiconductor die with back-side integrated inductive component
An integrated circuit (IC) that includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the...
US-1,003,2663 Anneal after trench sidewall implant to reduce defects
A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench...
US-1,003,2402 Power and brightness management of solid-state displays
System, method, and device for maximizing brightness of solid-state illuminators while minimizing power usage based on individual scene contents. An embodiment...
US-1,003,1875 Switch monitoring system
A switch monitoring system is provides information on sensor readings and contact closures over a one-wire network or a loop.
US-1,002,9908 Dielectric cladding of microelectromechanical systems (MEMS) elements for improved reliability
In described examples, a method of forming a microelectromechanical device comprises: forming a first metallic layer comprising a conducting layer on a...
US-1,002,8077 Avoidance of collisions and connection loss in network device serving multiple networks
A network device serving two or more networks using periodic times slots for transmission events is configured to determine that one of the periodic time slots...
US-1,002,7376 Guided near field communication for short range data communication
A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a...
US-1,002,7325 Circuit having a parallel voltage threshold architecture to support a wide voltage supply range
A circuit coupled to receive an input voltage that can span a wide voltage supply range and a voltage translator that includes the circuit are disclosed. The...
US-1,002,7295 Common mode gain trimming for amplifier
An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common...
US-1,002,6839 Epitaxial source/drain differential spacers
A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over...
US-1,002,6837 Embedded SiGe process for multi-threshold PMOS transistors
An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS...
US-1,002,6817 Low-stress low-hydrogen LPCVD silicon nitride
A microelectronic device contains a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000...
US-1,002,6815 Ultrashallow emitter formation using ALD and high temperature short time annealing
An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 110.sup.20 atoms/cm.sup.3, and...
US-1,002,6730 Single mask level including a resistor and a through-gate implant
A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a...
US-1,002,6712 ESD protection circuit with stacked ESD cells having parallel active shunt
An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first...
US-1,002,6706 Adding cap to copper passivation flow for electroless plating
An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated...
US-1,002,5955 Pipeline processor execution stages, secure emulation logic, gating debug/profile output
The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative...
US-1,002,5569 Linear-time algorithm to determine the maximum number of iterations of the iterative algorithm for data-flow...
A compiler converts a high level language program into a corresponding machine level language program. The compiler forms an initial control flow graph of the...
US-1,002,5560 Homogenous atomic pattern for double, add, and subtract operations for digital authentication using elliptic...
A method of performing finite field addition and doubling operations in an elliptic curve cryptography (ECC) authentication scheme as a countermeasure to...
US-1,002,4979 Photon counting with coincidence detection
A photon counting system includes a photon sensor and pixel circuitry. The pixel circuitry includes a charge sensitive amplifier (CSA), an analog to digital...
US-1,002,4929 Vapor cell structure having cavities connected by channels for micro-fabricated atomic clocks, magnetometers,...
A first apparatus includes a vapor cell having first and second cavities fluidly connected by multiple channels. The first cavity is configured to receive a...
US-1,002,4918 Cores, TAMS, TAM controllers, TAM selector, and scan router circuitry
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard...
US-1,002,4913 Tap commandable data register control router inverted TCK, TMS/TDI imputs
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
US-1,002,4912 One tap domain coupling two trace circuits, address command port
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI...
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