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Patent # Description
US-9,112,253 Dielectric waveguide combined with electrical cable
A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A...
US-9,112,011 FET dielectric reliability enhancement
A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the...
US-9,112,000 Method for ensuring DPT compliance for auto-routed via layers
A method of generating an integrated circuit with a double patterning technology (DPT) compatible via pattern using a reduced DPT compatible via design rule...
US-9,111,845 Integrated circuit package with printed circuit layer
An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.
US-9,111,779 IC resistor formed with integral heatsinking structure
A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to...
US-9,111,628 Read margin measurement in a read-only memory
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of...
US-9,111,536 Method and system to play background music along with voice on a CDMA network
A method and system for compressing an audio signal. The method includes receiving a segment of an audio signal and selectively disabling noise suppression for...
US-9,111,066 Clock tree design
A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an...
US-9,110,845 Memory management unit that applies rules based on privilege identifier
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on...
US-9,110,161 Antenna selection for GNSS receivers
Embodiments of the invention provide a system and method to improve the performance of a GNSS receiver using antenna switching. The system has a plurality of...
US-9,110,111 Methods and systems to determine a final value of random telegraph noise time constant and magnitude
A method includes, for a device and at each of a plurality of sampling frequencies, measuring a parameter of the device to generate a plurality of signals and...
US-9,106,533 Source and diversity rate equal to a first transmission rate
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
US-9,105,567 Making ESD diode with P-S/D overlying N-well and P-EPI portion
An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said...
US-9,104,217 Electronic device and method for generating a curvature compensated bandgap reference voltage
The invention relates to an electronic device with a bandgap reference generator including a first path with series connection of a first bipolar transistor, a...
US-9,103,916 Apparatus and method for indoor positioning
Apparatus and method for positioning a wireless device. In one embodiment, a method for indoor positioning includes determining a reference location of a...
US-9,103,886 Delay testing capturing second response to first response as stimulus
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and...
US-9,103,885 Integrated circuit with plural comparators receiving expected data and mask data from different pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-9,103,882 Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-9,103,881 Operating scan path generators and compactors sequentially and capturing simultaneously
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-9,102,511 Hermetic plastic molded MEMS device package and method of fabrication
A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110)...
US-9,102,296 Relay attack prevention for passive entry/passive start systems
A keyfob is disclosed for use in detecting an attack on a vehicle. The keyfob includes a microcontroller, a wake receiver and an accelerometer. The wake...
US-9,100,934 Channel quality report processes, circuits and systems
Coordinated multi-point (CoMP) transmissions in a cellular network is performed using multi-broadcast single frequency network (MBSFN) subframes. During CoMP...
US-9,100,152 Apparatus for dimensioning the control channel for transmission efficiency in communications systems
Embodiments of the invention provide methods for optimizing the spectral efficiency of control channel transmissions carrying scheduling assignments from a...
US-9,100,102 Method to use a preamble with band extension in power line communications
Embodiments include methods of powerline communications using a preamble with band extension is provided. A method may include receiving a packet data unit PDU....
US-9,100,035 Asynchronous sampling using a dynamically adustable snapback range
A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each...
US-9,100,021 Linear capacitively coupled touch sensor and method
A system includes a capacitively-coupled touch sensor having a conductive first layer and a conductive second layer on a first insulative layer. The width of...
US-9,100,010 Cascoded H-bridge pre-driver
An aspect of the present invention includes a circuit having a cascoded H-bridge, an upper voltage supply component, a lower voltage supply component and a...
US-9,099,998 Positive edge preset reset flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable...
US-9,099,944 Return control circuitry for VCM
To provide a disk drive capable of inhibiting the occurrence of acoustic noise caused by a voltage pulse when the head is retracted using a speed control method...
US-9,099,523 ESD protection circuit with isolated SCR for negative voltage operation
A semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108)...
US-9,098,438 Synchronized voltage scaling and device calibration
A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit...
US-9,098,148 Detecting and tracking touch on an illuminated surface using a machine learning classifier
A method for touch detection that is performed by a touch processor in an optical touch detection system is provided. The method includes receiving an image of...
US-9,097,764 Scan chain in an integrated circuit
In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where...
US-9,097,763 State machine shifting between idle, capture, shift 1, shift 2
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-9,094,248 Wireless system with hybrid automatic retransmission request in interference-limited communications
A wireless receiver for receiving signals from an interference-limited transmitter in an interference-limited system comprising at least one transmit antenna,...
US-9,094,234 Carrier sense multiple access (CSMA) protocols for power line communications (PLC)
Systems and methods for carrier sense multiple access (CSMA) protocols for power line communications (PLC) are described. In some embodiments, a method may...
US-9,094,184 First and second phase detectors and phase offset adder PLL
A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control...
US-9,094,172 Channel quality report processes, circuits and systems
An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a...
US-9,094,169 ACKNAK and CQI channel mapping schemes in wireless networks
A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to...
US-9,093,900 Measuring current in a power regulator system
One embodiment includes a power regulator system. The system includes a gate driver circuit configured to generate switching signal and a switching circuit...
US-9,093,555 Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon...
US-9,093,380 Dielectric liner added after contact etch before silicide formation
A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon,...
US-9,093,336 Determining optimum code from default, programmable, and test trim codes
In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting...
US-9,093,315 CMOS process to improve SRAM yield
An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall...
US-9,093,303 Spacer shaper formation with conformal dielectric film for void free PMD gap fill
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
US-9,093,301 Driver for normally on III-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
US-9,093,298 Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
US-9,092,228 Systems and methods for software instruction translation from a high-level language to a specialized...
A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when...
US-9,092,206 Microprocessor unit capable of multiple power modes having a register with direct control bits and register...
A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The...
US-9,091,736 Systems and methods of battery cell anomaly detection
Systems and methods for cell anomaly detection are provided. The disclosed systems and methods of cell anomaly detection may use a single circuit to detect both...
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