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Patent # Description
US-9,121,903 Parallel scan path distributor/collector controller having serial and control inputs
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these...
US-9,121,767 System clock counter counting ring oscillator pulses during programmed value
A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator....
US-9,121,714 Attitude estimation for pedestrian navigation using low cost MEMS accelerometer in mobile applications, and...
A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor...
US-9,121,106 Method of forming a laminated magnetic core with sputter deposited and electroplated layers
A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between...
US-9,119,321 Assembly method for converting the precursors to capacitors
A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor and an integrated circuit on a surface of a substrate....
US-9,118,342 Low power excess loop delay compensation technique for delta-sigma modulators
A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog...
US-9,118,315 Scheme to improve the performance and reliability in high voltage IO circuits designed using low voltage devices
A high voltage input/output (IO) circuit designed using low voltage devices. The IO circuit receives a first bias voltage and a second bias voltage. The IO...
US-9,118,259 Phase-shifted dual-bridge DC/DC converter with wide-range ZVS and zero circulating current
Disclosed is a family of new DC/DC converters and a new control method. The converter comprises two bridge inverters, two full-wave rectification circuits and a...
US-9,118,239 Power supply control method for constant current constant power control
A digital power supply and power supply controller are presented, including a voltage control loop and a current control loop, with a controller for pulse width...
US-9,117,775 Alignment to multiple layers
A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a...
US-9,117,691 Low cost transistors
An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the...
US-9,117,687 High voltage CMOS with triple gate oxide
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a...
US-9,117,535 Single sided bit line restore for power reduction
A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array....
US-9,117,106 Use of three-dimensional top-down views for business analytics
A method of analyzing a depth image in a digital system is provided that includes detecting a foreground object in a depth image, wherein the depth image is a...
US-9,116,830 Method to extend data retention for flash based storage in a real time device processed on generic...
This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention...
US-9,116,769 ASIP with reconfigurable circuitry implementing atomic operations of a PLL
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...
US-9,116,590 5-wire resistive touch screen pressure measurement circuit and method
A 5-wire touch screen system includes a touch screen (10) including a wiper (11) and a resistive layer (16) aligned with the wiper and first (UL), second (UR),...
US-9,116,209 Gating WSP update and TAP updatedr with TAP IR enable
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,...
US-9,116,208 Address and command port with tap and master controller circuitry
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI...
US-9,116,207 IC gating selection on first/second and deselection on second/third counts
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path....
US-9,114,995 Separating Metallic and Semiconductor SWNTS with sinusoidal dipole-inducing magnetic fields
A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a...
US-9,113,470 Systems and methods for network coding using maximum distance separable (MDS) linear network codes
A method for network coding includes generating a message matrix, where each column of the message matrix corresponds to one of K message packets and each...
US-9,113,460 Mapping between logical and physical uplink control resource blocks in wireless networks
A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations on an uplink channel in a wireless network. A...
US-9,113,398 Multirole device muxing channel scan with channel scan time slices
Systems and methods for channel scanning for multirole device are disclosed. One implementation relates to a method for servicing functions by a multirole...
US-9,113,340 Synchronized channel access in coexisting wireless networks
A system and method for arbitrating channel access in a wireless device including co-located network transceivers are disclosed herein. A wireless device...
US-9,113,325 Signaling of random access preamble time-frequency location in wireless networks
Embodiments of the present disclosure provide a base station sub-system, a method of allocating random access configurations and a method of downlink signaling...
US-9,112,916 Systems and methods for construction of and network coding using near-maximum distance separable (MDS) linear...
A method for network coding using a near-maximum distance separable linear network code includes generating a message matrix where each column of the message...
US-9,112,753 Interleaver design and header structure for ITU G.hnem
Embodiments of the invention provide an interleaver design and header fields for ITU-T G.hnem. The header may comprise two parts that are separately encoded. A...
US-9,112,527 Digital-to-analog sinusoidal driver apparatus, systems and methods
Input codes are sequenced at a lower-resolution linear DAC and the output is converted to a linear current waveform. A first of two interconnected analog...
US-9,112,413 Switched mode assisted linear regulator with AC coupling with capacitive charge control
The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load,...
US-9,112,409 Switched mode assisted linear regulator with dynamic buck turn-off using ZCD-controlled tub switching
A switched mode assisted linear regulator includes a linear amplifier (LA) and a buck converter configured as a current source. In example embodiments, the buck...
US-9,112,374 Converter and method for extracting maximum power from piezo vibration harvester
A system (1-2) for efficiently transferring harvested vibration energy to a battery (6) includes a piezo harvester (2) generating an AC output voltage...
US-9,112,253 Dielectric waveguide combined with electrical cable
A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A...
US-9,112,011 FET dielectric reliability enhancement
A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the...
US-9,112,000 Method for ensuring DPT compliance for auto-routed via layers
A method of generating an integrated circuit with a double patterning technology (DPT) compatible via pattern using a reduced DPT compatible via design rule...
US-9,111,845 Integrated circuit package with printed circuit layer
An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die.
US-9,111,779 IC resistor formed with integral heatsinking structure
A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to...
US-9,111,628 Read margin measurement in a read-only memory
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of...
US-9,111,536 Method and system to play background music along with voice on a CDMA network
A method and system for compressing an audio signal. The method includes receiving a segment of an audio signal and selectively disabling noise suppression for...
US-9,111,066 Clock tree design
A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an...
US-9,110,845 Memory management unit that applies rules based on privilege identifier
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on...
US-9,110,161 Antenna selection for GNSS receivers
Embodiments of the invention provide a system and method to improve the performance of a GNSS receiver using antenna switching. The system has a plurality of...
US-9,110,111 Methods and systems to determine a final value of random telegraph noise time constant and magnitude
A method includes, for a device and at each of a plurality of sampling frequencies, measuring a parameter of the device to generate a plurality of signals and...
US-9,106,533 Source and diversity rate equal to a first transmission rate
Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate...
US-9,105,567 Making ESD diode with P-S/D overlying N-well and P-EPI portion
An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said...
US-9,104,217 Electronic device and method for generating a curvature compensated bandgap reference voltage
The invention relates to an electronic device with a bandgap reference generator including a first path with series connection of a first bipolar transistor, a...
US-9,103,916 Apparatus and method for indoor positioning
Apparatus and method for positioning a wireless device. In one embodiment, a method for indoor positioning includes determining a reference location of a...
US-9,103,886 Delay testing capturing second response to first response as stimulus
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and...
US-9,103,885 Integrated circuit with plural comparators receiving expected data and mask data from different pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-9,103,882 Automatable scan partitioning for low power using external control
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
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