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Patent # Description
US-9,082,473 Power supply brownout protection circuit and method for embedded FRAM
Corruption of data in a FRAM (2) is avoided by applying a regulated voltage (V.sub.LDO) to a conductive pin (5-1). A switch (SW1) is coupled between the...
US-9,082,392 Method and apparatus for a configurable active noise canceller
A method and apparatus for active noise canceling. The method includes retrieving an input sample from at least one of a feedback or feedforward microphone...
US-9,081,064 IC scan cell coupled to TSV top and bottom contacts
An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between...
US-9,081,063 On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems
An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic...
US-9,081,059 Formatter selectively routing response data to stimulus data inputs
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and...
US-9,081,053 Using continuous sweep frequencies in a system frequency response test
A system and method for measuring the frequency response of a system under test using a single swept-frequency chirp signal. A tapered chirp-frequency test...
US-9,081,051 Methods for testing manufactured products
The problem of high test cost of manufactured goods can be partially solved by lowering the percentage of the goods to be tested methodically while keeping the...
US-9,079,002 Ceramic nanochannel drug delivery device and method of formation
A method of forming a drug delivery device includes laser forming a top ceramic plate to include an inner portion including top laser micromachined...
US-9,078,058 Applications for a two-way wireless speaker system
The two-way wireless speaker system of this invention increases sound fidelity by enabling speakers to acknowledge receipt of audio data packets. This provides...
US-9,078,001 Efficient bit-plane decoding algorithm
A bitplane decoding system where the bitplane operations are broken up into an optimized plurality of sub-tasks. A pipeline structure is established for the...
US-9,077,996 Predicted motion vectors
A video encoder includes an entropy encoder that computes a predicted motion vector (PMV) for each of a plurality of macroblocks in a video frame based on...
US-9,077,442 DSSS inverted spreading for smart utility networks
A method of operating a transmitter (FIGS. 3A and 5A) is disclosed. The method includes receiving a sequence of data bits (DATA), wherein each data bit has a...
US-9,077,360 Extension of ADC dynamic range using post-processing logic
An apparatus, comprising: an analog to digital converter including: a clipping detector; and a post-processor, wherein the post processor generates synchronous...
US-9,077,359 Asynchronous to synchronous sampling using modified akima algorithm
A method, comprising: selecting two Two-Tuples before and two after a selected synchronous ADC conversion point; calculating the coefficients of a third order...
US-9,077,327 Optimized peak detector for the AGC loop in a digital radio receiver
A method of peak detection applicable to complex in-phase and quadrature phase signals in a digital radio receiver where the incoming signal is divided into a...
US-9,076,891 Integrated circuit ("IC") assembly includes an IC die with a top metallization layer and a conductive epoxy...
An integrated circuit ("IC") assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end...
US-9,076,863 Semiconductor structure with a doped region between two deep trench isolation structures
The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation...
US-9,076,760 JFET having width defined by trench isolation
A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a...
US-9,076,671 Power integrated circuit including series-connected source substrate and drain substrate power mosfets
A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the...
US-9,076,670 Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and...
In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same...
US-9,076,557 Read margin measurement in a read-only memory
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of...
US-9,075,928 Hazard detection and elimination for coherent endpoint allowing out-of-order execution
A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is...
US-9,075,744 Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one...
This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two...
US-9,075,743 Managing bandwidth allocation in a processing node using distributed arbitration
Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate...
US-9,075,477 Touch panel apparatus and methods
Apparatus and methods process a set of calibration sample values acquired in response to a sequence of calibration touch events generated at known X-Y...
US-9,075,113 Linking module with IC and core TAP output enable leads
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-9,071,844 Motion estimation with motion vector penalty
The MPEG motion estimation process is improved by the introduction of the motion vector penalty. The motion vector employed to encode a macroblock takes into...
US-9,071,823 Method and apparatus for predictive reference data transfer scheme for motion estimation
A method and apparatus for predicting reference data transfer scheme for motion estimation. The method includes computing, via the processor, hypothetical...
US-9,070,785 High-k / metal gate CMOS transistors with TiN gates
An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25...
US-9,070,768 DMOS transistor having an increased breakdown voltage and method for production
A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor...
US-9,070,703 High speed digital interconnect and method
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
US-9,070,575 Integrated circuit with integrated decoupling capacitors
Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric...
US-9,069,073 Removing and de-weighting outlier measurements from satellite and previous information
Methods and integrated circuits for performing receiver autonomous integrity monitoring (RAIM) in global navigation satellite system (GNSS) receivers are...
US-9,066,110 Parsing friendly and error resilient merge flag coding in video coding
Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate...
US-9,066,055 Power supply architectures for televisions and other powered devices
A method includes transporting audio/video data using at least one signal line in a cable. The method also includes concurrently transporting at least about 100...
US-9,065,476 Two adjacent bit values switching current source between three paths
A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control...
US-9,065,430 Architecture for VBUS pulsing in UDSM processes
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of...
US-9,065,413 Method and apparatus for circuit with low IC power dissipation and high dynamic range
An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost...
US-9,064,903 Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The...
US-9,064,726 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,063,889 System and method for secure mode for processors and memories on multiple semiconductor dies within a single...
A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a...
US-9,063,559 Battery charger and method for collecting maximum power from energy harvester circuit
An energy harvesting system for transferring energy from an energy harvester (2) having an output impedance (Z.sub.i) to a DC-DC converter (10) includes a...
US-9,063,197 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,062,971 E-compass, tilt sensor, memory and processor with coarse detilting procedure
An electronic circuit includes an electronic compass having e-compass sensors mounted on different axes and operable to supply e-compass sensor data, memory...
US-9,059,881 Hexagonal constellations and decoding same in digital communication systems
Embodiments of the invention provide a method of decoding of hexagonal constellations. The decoding methods exploit the inherent structure of the hexagonal grid...
US-9,059,824 Joint processing down link coordinated multi-point reference signal support
This invention concerns multiplexing in Long Term Evolution (LTE) and Long Term Evolution-Advanced (LTE-A) in Evolved Universal Terrestrial Radio Access Network...
US-9,059,640 Control circuit for a buck power factor correction stage
This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in low cost, high efficiency power...
US-9,059,324 Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p-...
US-9,059,185 Copper leadframe finish for copper wire bonding
A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113)...
US-9,059,032 SRAM cell parameter optimization
An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage...
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