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Patent # Description
US-9,184,971 Apparatus for and method of robust packet detection and frequency offset estimation
A novel and useful apparatus for and method of packet detection and carrier frequency offset estimation. The packet detection mechanism is robust to channels...
US-9,184,967 System and method for generating frame structure for MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,184,794 Cyclic shift selection for MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,184,784 Method and apparatus for digital predistortion for a switched mode power amplifier
A method includes receiving an input signal and predistorting a baseband representation of the input signal at a carrier frequency and at one or more harmonic...
US-9,184,779 Dynamic medium switch in co-located PLC and RF networks
An electronic communication device comprises a first transceiver capable of a bi-directional communication session on a first communication medium; a second...
US-9,184,762 Mismatch profile
A system can include a signal image correlator receives a discrete frequency domain representation of a signal tone in an interleaved analog-to-digital (IADC)...
US-9,184,761 Asynchronous to synchronous sampling using Akima algorithm
A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third...
US-9,184,226 Embedded tungsten resistor
A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR...
US-9,184,163 Low cost transistors
An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the...
US-9,184,121 Stacked synchronous buck converter having chip embedded in outside recess of leadframe
A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and...
US-9,184,120 Nonleaded package and leadframe strip and method
A nonleaded IC package, such as a QFN, including an encapsulation block having at least one generally flat lateral sidewall surface; and a plurality of leads,...
US-9,184,119 Lead frame with abutment surface
A lead frame device may include an integral die pad member, two separate finger members, a central body portion, each of the finger members have a top and a...
US-9,183,873 Laser diode driver damping circuit
A damping circuit having an input terminal and an output terminal is described. The damping circuit comprises a driver having an input and an output; an RC...
US-9,183,084 Memory attribute sharing between differing cache levels of multilevel cache
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the...
US-9,182,493 Fine time assistance for global navigation satellite systems
Apparatus and method for providing fine timing assistance to global navigation satellite systems (GNSS) via wireless local area network (WLAN). In one...
US-9,182,453 Hall sensor excitation system
A Hall plate excitation system provides reduced offset and temperature dependence. The Hall plate excitation system includes a current source, a switching...
US-9,182,248 Power line communication network and discovery process
An apparatus for a power line communication network includes a power line transmitter/receiver, a processor coupled to the power line transmitter/receiver, and...
US-9,179,492 Electronic device, method and system for half duplex data transmission
An electronic device and method for half duplex data transmission in a long range keyless entry and go system, and more specifically to an RFID transponder, a...
US-9,179,362 Systems and methods for networking coding using Reed-Solomon codes
A method for network coding includes encoding a plurality of message packets to produce a plurality of encoded packets. Each message packet and each encoded...
US-9,179,112 Methods for combining camera and projector functions in a single device
Described are handheld devices with combined image capture and image projection functions. One embodiment includes modulating and capturing a light beam along...
US-9,178,589 Dual layer beam forming in cellular networks
Single user and multiuser MIMO transmission in a cellular network may be performed by selecting by a base station (eNB) to transmit either one or two...
US-9,178,525 Mismatch corrector
A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective...
US-9,178,499 Low-power offset-stored latch
A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset...
US-9,178,434 Integrated primary startup bias and MOSFET driver
Some implementations are directed to a A DC-to-DC converter that includes a power transformer having a primary side and a secondary side and a plurality of...
US-9,178,424 Switched mode DCDC converter efficiency improvement by adaptive driver stage
In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second...
US-9,178,422 Resonance-based single inductor output-driven DC-DC converter and method
A resonance-based DC-DC converter for converting a DC input voltage to a first DC output voltage (V.sub.OUT1) on a output conductor (9) includes an inductor (L)...
US-9,178,038 Raised source/drain MOS transistor and method of forming the transistor with an implant spacer and an epitaxial...
A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the...
US-9,178,037 Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
US-9,177,945 Packaged semiconductor device having multilevel leadframes configured as modules
Fabricating a packaged semiconductor device provides first planar leadframe with first leads and pads having attached electronic components. The first leadframe...
US-9,177,806 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,177,802 High tilt angle plus twist drain extension implant for CHC lifetime improvement
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one...
US-9,177,546 Cloud based adaptive learning for distributed sensors
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sound parameter information is extracted from...
US-9,176,556 Serial bus voltage compensation
A serial bus network includes a voltage regulator, a plurality of power switches, and a voltage monitor. The voltage regulator provides power to a plurality of...
US-9,176,316 Spatial light modulation display system
An improved spatial light modulation display system includes light sources for providing red, green, and blue light. A system controller includes functionality...
US-9,176,203 Apparatus and method for in situ current measurement in a conductor
Improved current sensing methods and apparatus and conductor apparatus are presented for sensing current in a bus bar or other conductor using one or more...
US-9,176,188 Waveform calibration using built in self test mechanism
A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the...
US-9,176,173 Method for detecting imperfect mounting of a rod-shaped metallic object in a metallic hollow shaft and a device
A method for detecting an imperfect mounting of an essentially rod-shaped metallic object in a metallic hollow shaft is provided. The imperfect mounting may...
US-9,172,517 Network power optimization via white lists
A device and method for controlling radio power in a wireless sensor network. A wireless sensor device includes a wireless transceiver, a white list generator,...
US-9,172,483 Signal quality estimation and control
Several circuits and methods implemented to perform signal quality estimation and control are disclosed. In an embodiment, a method of signal quality estimation...
US-9,172,431 Channel selection in power line communications
A power line communication (PLC) device comprises a processor and a memory coupled to the processor. The memory is configured to store program instructions...
US-9,172,243 Shut-off circuits for latched active ESD FET
An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD...
US-9,171,901 Method for improving device performance using dual stress liner boundary
An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates...
US-9,171,830 Fabricating a proximity sensor having light-blocking structure in leadframe
A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is...
US-9,171,828 DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and...
US-9,171,106 Apparatus and method to collect and condense design violations from output data files
A method includes searching a plurality of lines of a log file for a violation of a defined condition; creating a database of all discovered violations;...
US-9,170,956 System and method for virtual hardware memory protection
A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus...
US-9,170,889 Recovery from the loss of synchronization with finite state machines
The invention is a method of operating a system having multiple finite state machines and a controller. Each finite state machine enters an offline state upon...
US-9,170,680 Method, system and computer program product for operating a touchscreen
Within a display area of a touchscreen, multiple elements are displayed. A location is detected of a physical touch within the display area. In response to...
US-9,170,300 Linking circuitry selectively coupling TDI/TDO with first and second domains
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-9,170,299 DDR addressable TAP interface with shadow protocol and TAP domain
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface...
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