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Patent # Description
US-9,100,102 Method to use a preamble with band extension in power line communications
Embodiments include methods of powerline communications using a preamble with band extension is provided. A method may include receiving a packet data unit PDU....
US-9,100,035 Asynchronous sampling using a dynamically adustable snapback range
A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each...
US-9,100,021 Linear capacitively coupled touch sensor and method
A system includes a capacitively-coupled touch sensor having a conductive first layer and a conductive second layer on a first insulative layer. The width of...
US-9,100,010 Cascoded H-bridge pre-driver
An aspect of the present invention includes a circuit having a cascoded H-bridge, an upper voltage supply component, a lower voltage supply component and a...
US-9,099,998 Positive edge preset reset flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable...
US-9,099,944 Return control circuitry for VCM
To provide a disk drive capable of inhibiting the occurrence of acoustic noise caused by a voltage pulse when the head is retracted using a speed control method...
US-9,099,523 ESD protection circuit with isolated SCR for negative voltage operation
A semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108)...
US-9,098,438 Synchronized voltage scaling and device calibration
A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit...
US-9,098,148 Detecting and tracking touch on an illuminated surface using a machine learning classifier
A method for touch detection that is performed by a touch processor in an optical touch detection system is provided. The method includes receiving an image of...
US-9,097,764 Scan chain in an integrated circuit
In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where...
US-9,097,763 State machine shifting between idle, capture, shift 1, shift 2
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-9,094,248 Wireless system with hybrid automatic retransmission request in interference-limited communications
A wireless receiver for receiving signals from an interference-limited transmitter in an interference-limited system comprising at least one transmit antenna,...
US-9,094,234 Carrier sense multiple access (CSMA) protocols for power line communications (PLC)
Systems and methods for carrier sense multiple access (CSMA) protocols for power line communications (PLC) are described. In some embodiments, a method may...
US-9,094,184 First and second phase detectors and phase offset adder PLL
A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control...
US-9,094,172 Channel quality report processes, circuits and systems
An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a...
US-9,094,169 ACKNAK and CQI channel mapping schemes in wireless networks
A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to...
US-9,093,900 Measuring current in a power regulator system
One embodiment includes a power regulator system. The system includes a gate driver circuit configured to generate switching signal and a switching circuit...
US-9,093,555 Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon...
US-9,093,380 Dielectric liner added after contact etch before silicide formation
A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon,...
US-9,093,336 Determining optimum code from default, programmable, and test trim codes
In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting...
US-9,093,315 CMOS process to improve SRAM yield
An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall...
US-9,093,303 Spacer shaper formation with conformal dielectric film for void free PMD gap fill
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
US-9,093,301 Driver for normally on III-nitride transistors to get normally-off functionality
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
US-9,093,298 Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
US-9,092,228 Systems and methods for software instruction translation from a high-level language to a specialized...
A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when...
US-9,092,206 Microprocessor unit capable of multiple power modes having a register with direct control bits and register...
A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The...
US-9,091,736 Systems and methods of battery cell anomaly detection
Systems and methods for cell anomaly detection are provided. The disclosed systems and methods of cell anomaly detection may use a single circuit to detect both...
US-9,091,729 Scan chain masking qualification circuit shift register and bit-field decoders
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to...
US-9,091,728 Scan test controller with state machine and gates
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
US-9,090,991 Controlling an epitaxial growth process in an epitaxial reactor
A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as...
US-9,088,906 WiFi establishing a protected medium duration for USB-like wireless operations
A master electronic circuit includes a storage representing a wireless collision avoidance networking process involving collision avoidance overhead and...
US-9,088,334 Transceiver with asymmetric matching network
A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable...
US-9,088,324 Downlink 8 TX codebook sub-sampling for CSI feedback
This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook...
US-9,088,271 Dual-port positive level sensitive data retention latch
In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked...
US-9,088,261 Resonant impedance sensing based on controlled negative impedance
Resonant impedance sensing with a resonant sensor (such as LC) is based on generating a controlled negative impedance to maintain steady-state oscillation in...
US-9,088,211 Buck-boost converter with buck-boost transition switching control
A buck-boost regulation methodology operable, in one embodiment, with a single inductor, four-switch (S1-S4) buck-boost regulator configured for DCM. Buck-boost...
US-9,088,174 Adjusting voltage regulator operating parameters
Within an electronic device, a voltage regulator powers a load. The voltage regulator has adjustable operating parameters that can be set during operation of...
US-9,088,158 Reverse voltage condition protection in a power supply system
One embodiment includes a power system. The system includes a power switch device that is activated to provide an output voltage to a load in response to an...
US-9,087,918 Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer...
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the...
US-9,087,917 Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
US-9,087,867 Clam shell two-pin wafer holder for metal plating
A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the...
US-9,087,824 Use of dielectric slots for reducing via resistance in dual damascene process
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The...
US-9,087,708 IC with floating buried layer ring for isolation of embedded islands
An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of...
US-9,087,638 Wireless power system and method
A wireless power system and method are provided that employ a hybrid approach to adjusting transmission power to take advantages of the best features of...
US-9,087,586 TCAM with efficient multiple dimension range search capability
An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the...
US-9,087,585 TCAM with efficient range search capability
An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data...
US-9,086,887 Virtual register mode by designation of dedicated register as destination operand with switch connecting...
The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback...
US-9,084,319 Circuits and methods for reducing flicker in an LED light source
Method and circuits for balancing a first waveform used to drive an LED are disclosed herein. The first waveform has a first cycle with a first amplitude and a...
US-9,084,309 Digital phase angle detection and processing
Apparatus and methods operate to perform digital time sampling of a waveform associated with a rectified alternating current, edge-controlled power signal,...
US-9,084,242 On transparency of CoMP
This invention is a technique for coordinate multi-point wireless transmission between plural base stations and user equipment. At least one base station...
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