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Patent # Description
US-9,037,932 Position independent testing of circuits
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
US-9,036,683 Mitigation circuitry generating cross correlation doppler/code LAG variable comparison value
A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes...
US-9,036,614 PHY layer parameters for body area network (BAN) devices
In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN)...
US-9,036,609 Systems and methods for silencing wireless devices
Embodiments provide systems and methods to optimize the time when to receive transmissions from dissimilar wireless networks, and hence, improve the overall...
US-9,035,813 Technique for excess loop delay compensation in delta-sigma modulators
A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog...
US-9,035,706 Variability and aging sensor for integrated circuits
A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of...
US-9,035,458 Low resistance stacked annular contact
An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting...
US-9,035,422 Multilayer high voltage isolation barrier in an integrated circuit
A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil...
US-9,035,399 Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a...
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative...
US-9,035,352 Twin-well lateral silicon controlled rectifier
A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the...
US-9,035,318 Avalanche energy handling capable III-nitride transistors
A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a...
US-9,032,265 IC test adapter circuitry having scan control register bits
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to...
US-9,031,321 Content adaptive edge and detail enhancement for image and video processing
A content-adaptive edge and detail enhancement apparatus is described for image/video processing. Both 2D peaking and LTI/CTI are used in sharpening pictures....
US-9,031,137 Signaling signed band offset values for sample adaptive offset (SAO) filtering in video coding
A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band...
US-9,030,932 Enhanced carrier sense multiple access (CSMA) protocols
Systems and methods for enhanced carrier sense multiple access (CSMA) protocols are described. In various implementations, these systems and methods may be...
US-9,030,908 Programmable wavelet tree
An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to...
US-9,030,369 Terminationless power splitter/combiner
An apparatus is provided. First and second hybrid couplers are provided with each having a first port, a second port, a third port, a fourth port and with each...
US-9,030,356 Positioning system receiver sensor system coupled with measurement data output
Embodiments of the disclosure provide a cross coupled position engine architecture for sensor integration in a Global Navigation Satellite System. In one...
US-9,030,216 Coaxial four-point probe for low resistance measurements
Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one...
US-9,030,051 Wireless power transmission with improved modulation ripple
A wireless power receiver receives electrical power via electromagnetic field coupling from a wireless power transmitter. During communication time periods, the...
US-9,030,023 Bond pad stack for transistors
A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole...
US-9,029,990 Integrated circuit package
An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a...
US-9,029,263 Method of printing multiple structure widths using spacer double patterning
An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear...
US-9,029,251 Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment...
US-9,029,194 Making an integrated circuit module with dual leadframes
A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of...
US-9,026,861 Debug trace stream timestamping using downstream correlation
A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a...
US-9,025,773 Undetectable combining of nonaligned concurrent signals
The approach shown provides for an efficient implementation of time response, level response and frequency response alignment between two audio sources such as...
US-9,025,705 Current reduction in digital circuits
A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including...
US-9,025,675 Systems and methods for reducing blocking artifacts
Several systems, methods and integrated circuits capable of reducing blocking artifacts in video data are disclosed. In an embodiment, a system for reducing...
US-9,025,586 Secondary synchronization signal mapping
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter or a receiver. In one embodiment, the transmitter...
US-9,025,260 System and method for illuminating a target
According to one embodiment of the present invention, a system for illuminating a target includes a light source configured to emit one or more light beams with...
US-9,024,670 System and method for controlling circuit input-output timing
An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The...
US-9,024,600 PWM control apparatus for average output current balancing in multi-stage DC-DC converters
Pulse width modulation controller apparatus and techniques are presented for balancing output currents of DC-DC converter stages in a multi-stage DC-DC...
US-9,024,593 Power supply unit and a method for operating the same
A power supply unit includes a boost converter having an input node and output node. The output node is coupled to a high-side of an H-bridge that is for...
US-9,024,450 Two-track cross-connect in double-patterned structure using rectangular via
An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect...
US-9,024,397 Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure
A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where...
US-9,024,384 Indium, carbon and halogen doping for PMOS transistors
A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon...
US-9,023,289 System and method for production of high purity silicon solids and solids therefrom
Systems and methods and resulting compositions of matter including silicon solids from a mixture of silicon and water. The mixture is collected at a collection...
US-9,021,322 Probeless testing of pad buffers on wafer
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-9,021,320 pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the...
US-9,021,292 Method and system for asynchronous serial communication in a ring network by generating an oversampling clock...
Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial...
US-9,021,283 Processor having real-time power conservation
An apparatus having a processing unit and a monitor for monitoring activity associated with said processing unit. The monitor enables selective lowering of the...
US-9,021,170 System and method for improving ECC enabled memory timing
A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes...
US-9,020,459 Power saving receiver circuits, systems and processes
An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control...
US-9,020,454 Linearization and calibration predistortion of a digitally controlled power amplifier
An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion...
US-9,019,670 Bi-directional ESD protection circuit
A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor...
US-9,019,004 System and method for distributed regulation of charge pumps
A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control...
US-9,018,976 Dual-port positive level sensitive reset preset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch....
US-9,018,923 Dynamic bias soft start control apparatus and methods
Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the...
US-9,018,800 High efficiency wide load range buck/boost/bridge photovoltaic micro-converter
Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the...
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