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Patent # Description
US-9,076,863 Semiconductor structure with a doped region between two deep trench isolation structures
The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation...
US-9,076,760 JFET having width defined by trench isolation
A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a...
US-9,076,671 Power integrated circuit including series-connected source substrate and drain substrate power mosfets
A semiconductor device containing a high voltage MOS transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the...
US-9,076,670 Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and...
In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same...
US-9,076,557 Read margin measurement in a read-only memory
Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of...
US-9,075,928 Hazard detection and elimination for coherent endpoint allowing out-of-order execution
A coherence maintenance address queue tracks each memory access from receipt until the memory reports the access complete. The address of each new access is...
US-9,075,744 Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one...
This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two...
US-9,075,743 Managing bandwidth allocation in a processing node using distributed arbitration
Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate...
US-9,075,477 Touch panel apparatus and methods
Apparatus and methods process a set of calibration sample values acquired in response to a sequence of calibration touch events generated at known X-Y...
US-9,075,113 Linking module with IC and core TAP output enable leads
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-9,071,844 Motion estimation with motion vector penalty
The MPEG motion estimation process is improved by the introduction of the motion vector penalty. The motion vector employed to encode a macroblock takes into...
US-9,071,823 Method and apparatus for predictive reference data transfer scheme for motion estimation
A method and apparatus for predicting reference data transfer scheme for motion estimation. The method includes computing, via the processor, hypothetical...
US-9,070,785 High-k / metal gate CMOS transistors with TiN gates
An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25...
US-9,070,768 DMOS transistor having an increased breakdown voltage and method for production
A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor...
US-9,070,703 High speed digital interconnect and method
In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue....
US-9,070,575 Integrated circuit with integrated decoupling capacitors
Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric...
US-9,069,073 Removing and de-weighting outlier measurements from satellite and previous information
Methods and integrated circuits for performing receiver autonomous integrity monitoring (RAIM) in global navigation satellite system (GNSS) receivers are...
US-9,066,110 Parsing friendly and error resilient merge flag coding in video coding
Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate...
US-9,066,055 Power supply architectures for televisions and other powered devices
A method includes transporting audio/video data using at least one signal line in a cable. The method also includes concurrently transporting at least about 100...
US-9,065,476 Two adjacent bit values switching current source between three paths
A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control...
US-9,065,430 Architecture for VBUS pulsing in UDSM processes
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of...
US-9,065,413 Method and apparatus for circuit with low IC power dissipation and high dynamic range
An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost...
US-9,064,903 Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The...
US-9,064,726 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,063,889 System and method for secure mode for processors and memories on multiple semiconductor dies within a single...
A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a...
US-9,063,559 Battery charger and method for collecting maximum power from energy harvester circuit
An energy harvesting system for transferring energy from an energy harvester (2) having an output impedance (Z.sub.i) to a DC-DC converter (10) includes a...
US-9,063,197 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,062,971 E-compass, tilt sensor, memory and processor with coarse detilting procedure
An electronic circuit includes an electronic compass having e-compass sensors mounted on different axes and operable to supply e-compass sensor data, memory...
US-9,059,881 Hexagonal constellations and decoding same in digital communication systems
Embodiments of the invention provide a method of decoding of hexagonal constellations. The decoding methods exploit the inherent structure of the hexagonal grid...
US-9,059,824 Joint processing down link coordinated multi-point reference signal support
This invention concerns multiplexing in Long Term Evolution (LTE) and Long Term Evolution-Advanced (LTE-A) in Evolved Universal Terrestrial Radio Access Network...
US-9,059,640 Control circuit for a buck power factor correction stage
This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in low cost, high efficiency power...
US-9,059,324 Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p-...
US-9,059,185 Copper leadframe finish for copper wire bonding
A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113)...
US-9,059,032 SRAM cell parameter optimization
An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage...
US-9,058,126 Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of...
US-9,057,615 Systems and methods for navigating using corrected yaw bias values
A method for navigating using a speed sensor and a yaw rate sensor includes computing, for each of a plurality of error parameter values, a distance traveled...
US-9,056,767 Dynamic access point based positioning
A wireless device that includes an access point (AP) scanner, a transceiver, and a controller coupled to the AP scanner and transceiver. The AP scanner is...
US-9,056,764 Microelectromechanical device packages with integral heaters
A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The...
US-9,055,301 Changing motion estimation precision to maintain encoding within desired time
A system comprising a processor and a compression module coupled to the processor. The compression module is adapted to perform motion estimation on video data...
US-9,055,227 Scene adaptive brightness/contrast enhancement
A method for brightness and contrast enhancement includes computing a luminance histogram of a digital image, computing first distances from the luminance...
US-9,054,736 Method and apparatus for analog to digital conversion
An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes...
US-9,054,695 Technique to realize high voltage IO driver in a low voltage BiCMOS process
An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a...
US-9,054,657 Reducing a settling time after a slew condition in an amplifier
In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential...
US-9,054,627 Method and apparatus to drive a linear resonant actuator at its resonant frequency
A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off...
US-9,054,294 Soft mechanical stops to limit over-travel of proof masses in cantilevered piezoelectric devices
A piezoelectric device is disclosed which has a built-in soft stop which serves for protection against excessive force.
US-9,054,214 Methodology of forming CMOS gates on the secondary axis using double-patterning technique
An integrated circuit containing core transistors and I/O transistors oriented perpendicular to the core transistors is formed by exposing a gate etch mask...
US-9,054,158 Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a...
The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the...
US-9,054,092 Method and apparatus for stopping resin bleed and mold flash on integrated circuit lead finishes
A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the...
US-9,054,071 Method to form stepped dielectric for field plate formation
A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field...
US-9,054,056 Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment...
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