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Accelerating scan test by re-using response data as stimulus data abstract
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
Managing power of thread pipelines according to clock frequency and
voltage specified in thread registers
A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions;...
Vector math instruction execution by DSP processor approximating division
and complex number magnitude
A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication...
Method for infrastructure messaging
A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration...
Clock drift compensation interpolator adjusting buffer read and write
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming...
Bi-phase communication demodulation techniques
One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to...
Method and apparatus for region-based weighted prediction with improved
global brightness detection
Described herein are a method and apparatus for determining a region-based weighted prediction with improved global brightness detection. The method includes...
Communication on a pilot wire
Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). In an...
Wireless communications with frequency band selection
A probe, listen and select (PLS) technique can be used to select from an available frequency spectrum a frequency band whose communication quality is suitable...
High speed dynamic comparator
A comparator circuit (FIG. 4) is disclosed. The circuit includes an amplifier circuit (300,302) arranged to produce an output signal (Vom,Vop). A first current...
Track and hold architecture with tunable bandwidth
To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth...
Charge pump circuit
A charge pump circuit includes a plurality of serially coupled stages and a plurality of clock drivers. A voltage output of a first of the stages is connected...
Circuits for improving linearity of metal oxide semiconductor (MOS)
Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region...
Dual-port negative level sensitive reset data retention latch
In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is...
Dual-port negative level sensitive data retention latch
In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked...
Tracking energy consumption using a fly-back converter technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
Hall effect device having voltage based biasing for temperature
A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device...
Reverse current protection control for a motor
A method is provided. A command to correspond to a target speed of a motor is received. A rotational speed of the motor is measured, and a brake-to-off ratio...
LED control system with a constant reference current
One embodiment includes a light-emitting diode (LED) control system. The system includes an LED driver system configured to regulate a control voltage based on...
High pin count, small SON/QFN packages
A plastic SON/QFN package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package;...
Integrated circuit package and method of making
An integrated circuit ("IC") device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger...
Etching method using an at least semi-solid media
An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively...
IC class T0-T2 taps with and without topology selection logic
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
Adapter circuitry resetting scan test logic to mandatory feature set
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
pBIST engine with distributed data logging
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not...
Prefetch address hit prediction to reduce memory access latency
A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined...
Non-blocking, pipelined write allocates with allocate data merging in a
multi-level cache system
This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache...
System and method for controlling aberrant transceiver operation
A transceiver and a method of controlling aberrant transceiver operation. In one embodiment, the transceiver includes: (1) a processor, (2) an interrupt system...
MAC protocols with subbanding
Systems and methods for designing, using, and/or implementing media access control (MAC) protocols with subbanding are described. In some embodiments, a method...
Device for operating using multiple protocols in wireless networks
A network includes an access point using a first protocol and a station using both the first protocol and a second protocol. The station uses the first protocol...
Partial CQI feedback in wireless networks
Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an...
Baseline capacitance calibration
An embodiment of the invention provides a method of creating a statistical model of a baseline capacitance C.sub.P of a capacitive sensor located on a...
Sampling rate based adaptive analog biasing
A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a...
Negative edge reset flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable...
Dual-port positive level sensitive preset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is...
Radiation induced diode structure
A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an...
High sheet resistor in CMOS flow
An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with...
Bipolar transistor having sinker diffusion under a trench
A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench...
Multi-landing contact etching
A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a...
High voltage polymer dielectric capacitor isolation device
An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed...
High voltage hybrid polymeric-ceramic dielectric capacitor
An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon...
Selective leadframe planishing
A method for fabricating a leadframe strip is disclosed. A leadframe pattern is formed from flat sheet of base metal. Additional metal layers are plated on...
Simple scatterometry structure for Si recess etch control
Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in...
Piezoelectric thin film process
A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity,...
Software breakpoints with tailoring for multiple processor shared memory
or multiple thread systems
The present invention provides methods for executing instructions in a processor to facilitate the debugging of digital systems. In these methods, a halt...
Optimizing memory usage and system performance in a file system requiring
entire blocks to be erased for...
A file system which ensures that some of the (desired) files ("linear files") are stored in corresponding exclusive blocks (i.e., a block that stores data...
Partial-writes to ECC (error check code) enabled memories
A memory system includes a memory and a memory controller coupled to the memory. The memory controller includes a data buffer configured to store a full data...
Compressor inputs from scan register output and input through flip-flop
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device...
IC test circuitry with tri-state buffer, comparator, and scan cell
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
Level one data cache line lock and enhanced snoop protocol during cache
victims and writebacks to maintain...
This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines....