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Patent # Description
US-9,054,027 III-nitride device and method having a gate isolating structure
A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional...
US-9,053,966 Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels
An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS...
US-9,053,799 Optimizing fuseROM usage for memory repair
A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each...
US-9,053,371 Method, system and computer program product for identifying a location of an object within a video sequence
In response to detecting a motion within a video sequence, a determination is made of whether the motion is a particular type of movement. In response to...
US-9,053,273 IC delaying flip-flop output partial clock cycle for equalizing current
Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data...
US-9,052,362 Scan test port capture/shift signals maintaining/transitioning sequence and idle states
Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a...
US-9,052,361 Wired-or fail flag in serial stimulus, expected/mask data test circuitry
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
US-9,052,360 Test circuit allowing precision analysis of delta performance degradation between two logic chains
A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate...
US-9,050,764 Low cost window production for hermetically sealed optical packages
Disclosed embodiments demonstrate batch processing methods for producing optical windows for microdevices. The windows protect the active elements of the...
US-9,049,408 Color space appearance model video processor
A method of color processing determines whether a pixel color is within at least one range of predetermined colors corresponding to a viewer expected color. If...
US-9,048,918 Antenna grouping and group-based enhancements for MIMO systems
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-9,048,910 Downlink 8 TX codebook sub-sampling for CSI feedback
This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook...
US-9,048,728 Switch pairs between resistor network and high/low DC converter comparator input
Two hysteresis levels, a high level and a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as...
US-9,048,297 Contact and via interconnects using metal around dielectric pillars
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars....
US-9,048,180 Low stress sacrificial cap layer
A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low...
US-9,048,151 Self-powered integrated circuit with photovoltaic cell
A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment,...
US-9,047,406 Maintaining coherent synchronization between data streams on detection of overflow
Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync...
US-9,047,188 State machine based parsing algorithm on a data-status FIFO with multiple banks
In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO...
US-9,047,140 Independently timed multiplier
An independently timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path....
US-9,047,121 System and method for scheduling jobs in a multi-core processor
A multi-core processor, comprising a plurality of processor cores to process jobs, a multicore navigator coupled to the plurality of processor cores to evaluate...
US-9,047,069 Computer implemented method of electing K extreme entries from a list using separate section comparisons
A computer implemented method selects K extreme elements of a list of N elements by partitioning each of the N elements into a plurality of sections. For each...
US-9,046,575 TAP test clock control circuitry connected to device address port
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without...
US-9,046,571 Tap with test compression architecture and start bit detector circuit
The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with...
US-9,043,664 I/O linking, TAP selection and multiplexer remove select control circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that...
US-9,043,286 IC updating file system meta data with log record data
A computer device (2010) with a file system having clusters and meta data. The computer device (2010) includes a processor (1030) and a storage (1025) coupled...
US-9,042,487 Blind I/Q mismatch compensation with receiver non-linearity
Apparatus and methods disclosed herein perform gain, clipping, and phase compensation in the presence of I/Q mismatch in quadrature RF receivers. Gain and phase...
US-9,042,480 Precoding codebook design for single user MIMO
A transmitter is for use with multiple transmit antennas and includes a precoder unit configured to precode data for a transmission using a precoding matrix...
US-9,042,173 Efficient memory sense architecture
Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense...
US-9,041,601 GNSS state machine searching received signal, moving bits, updating registers
Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a...
US-9,041,458 Universal filter implementing second-order transfer function
An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and...
US-9,040,854 MEMS electrostatic actuator
A MEMS electrostatic actuator includes a bottom plate affixed to a substrate and a top plate suspended above the bottom plate. The top plate has a parallel...
US-9,039,427 Interdigitated chip capacitor assembly
An interdigitated chip capacitor ("IDC") assembly including an IDC having a semiconductor block with a top portion, a bottom portion opposite the top portion, a...
US-9,037,932 Position independent testing of circuits
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
US-9,036,683 Mitigation circuitry generating cross correlation doppler/code LAG variable comparison value
A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes...
US-9,036,614 PHY layer parameters for body area network (BAN) devices
In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN)...
US-9,036,609 Systems and methods for silencing wireless devices
Embodiments provide systems and methods to optimize the time when to receive transmissions from dissimilar wireless networks, and hence, improve the overall...
US-9,035,813 Technique for excess loop delay compensation in delta-sigma modulators
A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog...
US-9,035,706 Variability and aging sensor for integrated circuits
A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of...
US-9,035,458 Low resistance stacked annular contact
An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting...
US-9,035,422 Multilayer high voltage isolation barrier in an integrated circuit
A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil...
US-9,035,399 Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a...
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative...
US-9,035,352 Twin-well lateral silicon controlled rectifier
A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the...
US-9,035,318 Avalanche energy handling capable III-nitride transistors
A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a...
US-9,032,265 IC test adapter circuitry having scan control register bits
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to...
US-9,031,321 Content adaptive edge and detail enhancement for image and video processing
A content-adaptive edge and detail enhancement apparatus is described for image/video processing. Both 2D peaking and LTI/CTI are used in sharpening pictures....
US-9,031,137 Signaling signed band offset values for sample adaptive offset (SAO) filtering in video coding
A method for signaling sample adaptive offset (SAO) band offset syntax elements in a video encoder is provided that includes receiving a plurality of band...
US-9,030,932 Enhanced carrier sense multiple access (CSMA) protocols
Systems and methods for enhanced carrier sense multiple access (CSMA) protocols are described. In various implementations, these systems and methods may be...
US-9,030,908 Programmable wavelet tree
An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to...
US-9,030,369 Terminationless power splitter/combiner
An apparatus is provided. First and second hybrid couplers are provided with each having a first port, a second port, a third port, a fourth port and with each...
US-9,030,356 Positioning system receiver sensor system coupled with measurement data output
Embodiments of the disclosure provide a cross coupled position engine architecture for sensor integration in a Global Navigation Satellite System. In one...
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