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Patent # Description
US-9,066,055 Power supply architectures for televisions and other powered devices
A method includes transporting audio/video data using at least one signal line in a cable. The method also includes concurrently transporting at least about 100...
US-9,065,476 Two adjacent bit values switching current source between three paths
A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control...
US-9,065,430 Architecture for VBUS pulsing in UDSM processes
Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of...
US-9,065,413 Method and apparatus for circuit with low IC power dissipation and high dynamic range
An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost...
US-9,064,903 Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The...
US-9,064,726 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,063,889 System and method for secure mode for processors and memories on multiple semiconductor dies within a single...
A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a...
US-9,063,559 Battery charger and method for collecting maximum power from energy harvester circuit
An energy harvesting system for transferring energy from an energy harvester (2) having an output impedance (Z.sub.i) to a DC-DC converter (10) includes a...
US-9,063,197 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,062,971 E-compass, tilt sensor, memory and processor with coarse detilting procedure
An electronic circuit includes an electronic compass having e-compass sensors mounted on different axes and operable to supply e-compass sensor data, memory...
US-9,059,881 Hexagonal constellations and decoding same in digital communication systems
Embodiments of the invention provide a method of decoding of hexagonal constellations. The decoding methods exploit the inherent structure of the hexagonal grid...
US-9,059,824 Joint processing down link coordinated multi-point reference signal support
This invention concerns multiplexing in Long Term Evolution (LTE) and Long Term Evolution-Advanced (LTE-A) in Evolved Universal Terrestrial Radio Access Network...
US-9,059,640 Control circuit for a buck power factor correction stage
This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in low cost, high efficiency power...
US-9,059,324 Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p-...
US-9,059,185 Copper leadframe finish for copper wire bonding
A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113)...
US-9,059,032 SRAM cell parameter optimization
An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage...
US-9,058,126 Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of...
US-9,057,615 Systems and methods for navigating using corrected yaw bias values
A method for navigating using a speed sensor and a yaw rate sensor includes computing, for each of a plurality of error parameter values, a distance traveled...
US-9,056,767 Dynamic access point based positioning
A wireless device that includes an access point (AP) scanner, a transceiver, and a controller coupled to the AP scanner and transceiver. The AP scanner is...
US-9,056,764 Microelectromechanical device packages with integral heaters
A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The...
US-9,055,301 Changing motion estimation precision to maintain encoding within desired time
A system comprising a processor and a compression module coupled to the processor. The compression module is adapted to perform motion estimation on video data...
US-9,055,227 Scene adaptive brightness/contrast enhancement
A method for brightness and contrast enhancement includes computing a luminance histogram of a digital image, computing first distances from the luminance...
US-9,054,736 Method and apparatus for analog to digital conversion
An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes...
US-9,054,695 Technique to realize high voltage IO driver in a low voltage BiCMOS process
An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a...
US-9,054,657 Reducing a settling time after a slew condition in an amplifier
In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential...
US-9,054,627 Method and apparatus to drive a linear resonant actuator at its resonant frequency
A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off...
US-9,054,294 Soft mechanical stops to limit over-travel of proof masses in cantilevered piezoelectric devices
A piezoelectric device is disclosed which has a built-in soft stop which serves for protection against excessive force.
US-9,054,214 Methodology of forming CMOS gates on the secondary axis using double-patterning technique
An integrated circuit containing core transistors and I/O transistors oriented perpendicular to the core transistors is formed by exposing a gate etch mask...
US-9,054,158 Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a...
The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the...
US-9,054,092 Method and apparatus for stopping resin bleed and mold flash on integrated circuit lead finishes
A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the...
US-9,054,071 Method to form stepped dielectric for field plate formation
A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field...
US-9,054,056 Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment...
US-9,054,027 III-nitride device and method having a gate isolating structure
A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional...
US-9,053,966 Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels
An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS...
US-9,053,799 Optimizing fuseROM usage for memory repair
A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each...
US-9,053,371 Method, system and computer program product for identifying a location of an object within a video sequence
In response to detecting a motion within a video sequence, a determination is made of whether the motion is a particular type of movement. In response to...
US-9,053,273 IC delaying flip-flop output partial clock cycle for equalizing current
Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data...
US-9,052,362 Scan test port capture/shift signals maintaining/transitioning sequence and idle states
Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a...
US-9,052,361 Wired-or fail flag in serial stimulus, expected/mask data test circuitry
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
US-9,052,360 Test circuit allowing precision analysis of delta performance degradation between two logic chains
A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate...
US-9,050,764 Low cost window production for hermetically sealed optical packages
Disclosed embodiments demonstrate batch processing methods for producing optical windows for microdevices. The windows protect the active elements of the...
US-9,049,408 Color space appearance model video processor
A method of color processing determines whether a pixel color is within at least one range of predetermined colors corresponding to a viewer expected color. If...
US-9,048,918 Antenna grouping and group-based enhancements for MIMO systems
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the...
US-9,048,910 Downlink 8 TX codebook sub-sampling for CSI feedback
This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook...
US-9,048,728 Switch pairs between resistor network and high/low DC converter comparator input
Two hysteresis levels, a high level and a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as...
US-9,048,297 Contact and via interconnects using metal around dielectric pillars
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars....
US-9,048,180 Low stress sacrificial cap layer
A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low...
US-9,048,151 Self-powered integrated circuit with photovoltaic cell
A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment,...
US-9,047,406 Maintaining coherent synchronization between data streams on detection of overflow
Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync...
US-9,047,188 State machine based parsing algorithm on a data-status FIFO with multiple banks
In the L2 FIFO architecture incoming frames are stored in a multi bank FIFO to enable offloading the programmable real-time unit to do other tasks. The L2 FIFO...
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