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Patent # Description
US-9,030,216 Coaxial four-point probe for low resistance measurements
Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one...
US-9,030,051 Wireless power transmission with improved modulation ripple
A wireless power receiver receives electrical power via electromagnetic field coupling from a wireless power transmitter. During communication time periods, the...
US-9,030,023 Bond pad stack for transistors
A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole...
US-9,029,990 Integrated circuit package
An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a...
US-9,029,263 Method of printing multiple structure widths using spacer double patterning
An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear...
US-9,029,251 Transistor performance using a two-step damage anneal
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment...
US-9,029,194 Making an integrated circuit module with dual leadframes
A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of...
US-9,026,861 Debug trace stream timestamping using downstream correlation
A method of correlating the timing of multiple interleaved trace data streams. A Time Stamp Trace stream logic monitors the event trace stream for a...
US-9,025,773 Undetectable combining of nonaligned concurrent signals
The approach shown provides for an efficient implementation of time response, level response and frequency response alignment between two audio sources such as...
US-9,025,705 Current reduction in digital circuits
A digital circuit includes at least one input node, a biasing circuit, and a digital baseband circuit. The input node receives a digital signal including...
US-9,025,675 Systems and methods for reducing blocking artifacts
Several systems, methods and integrated circuits capable of reducing blocking artifacts in video data are disclosed. In an embodiment, a system for reducing...
US-9,025,586 Secondary synchronization signal mapping
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter or a receiver. In one embodiment, the transmitter...
US-9,025,260 System and method for illuminating a target
According to one embodiment of the present invention, a system for illuminating a target includes a light source configured to emit one or more light beams with...
US-9,024,670 System and method for controlling circuit input-output timing
An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The...
US-9,024,600 PWM control apparatus for average output current balancing in multi-stage DC-DC converters
Pulse width modulation controller apparatus and techniques are presented for balancing output currents of DC-DC converter stages in a multi-stage DC-DC...
US-9,024,593 Power supply unit and a method for operating the same
A power supply unit includes a boost converter having an input node and output node. The output node is coupled to a high-side of an H-bridge that is for...
US-9,024,450 Two-track cross-connect in double-patterned structure using rectangular via
An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect...
US-9,024,397 Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure
A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where...
US-9,024,384 Indium, carbon and halogen doping for PMOS transistors
A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon...
US-9,023,289 System and method for production of high purity silicon solids and solids therefrom
Systems and methods and resulting compositions of matter including silicon solids from a mixture of silicon and water. The mixture is collected at a collection...
US-9,021,322 Probeless testing of pad buffers on wafer
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-9,021,320 pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the...
US-9,021,292 Method and system for asynchronous serial communication in a ring network by generating an oversampling clock...
Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial...
US-9,021,283 Processor having real-time power conservation
An apparatus having a processing unit and a monitor for monitoring activity associated with said processing unit. The monitor enables selective lowering of the...
US-9,021,170 System and method for improving ECC enabled memory timing
A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes...
US-9,020,459 Power saving receiver circuits, systems and processes
An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control...
US-9,020,454 Linearization and calibration predistortion of a digitally controlled power amplifier
An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion...
US-9,019,670 Bi-directional ESD protection circuit
A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor...
US-9,019,004 System and method for distributed regulation of charge pumps
A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control...
US-9,018,976 Dual-port positive level sensitive reset preset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch....
US-9,018,923 Dynamic bias soft start control apparatus and methods
Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the...
US-9,018,800 High efficiency wide load range buck/boost/bridge photovoltaic micro-converter
Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the...
US-9,015,544 Accelerating scan test by re-using response data as stimulus data abstract
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-9,015,504 Managing power of thread pipelines according to clock frequency and voltage specified in thread registers
A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions;...
US-9,015,452 Vector math instruction execution by DSP processor approximating division and complex number magnitude
A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication...
US-9,015,376 Method for infrastructure messaging
A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration...
US-9,014,321 Clock drift compensation interpolator adjusting buffer read and write clocks
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming...
US-9,014,305 Bi-phase communication demodulation techniques
One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to...
US-9,014,271 Method and apparatus for region-based weighted prediction with improved global brightness detection
Described herein are a method and apparatus for determining a region-based weighted prediction with improved global brightness detection. The method includes...
US-9,014,247 Communication on a pilot wire
Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). In an...
US-9,014,205 Wireless communications with frequency band selection
A probe, listen and select (PLS) technique can be used to select from an available frequency spectrum a frequency band whose communication quality is suitable...
US-9,013,344 High speed dynamic comparator
A comparator circuit (FIG. 4) is disclosed. The circuit includes an amplifier circuit (300,302) arranged to produce an output signal (Vom,Vop). A first current...
US-9,013,339 Track and hold architecture with tunable bandwidth
To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth...
US-9,013,229 Charge pump circuit
A charge pump circuit includes a plurality of serially coupled stages and a plurality of clock drivers. A voltage output of a first of the stages is connected...
US-9,013,226 Circuits for improving linearity of metal oxide semiconductor (MOS) transistors
Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region...
US-9,013,218 Dual-port negative level sensitive reset data retention latch
In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is...
US-9,013,217 Dual-port negative level sensitive data retention latch
In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked...
US-9,013,203 Tracking energy consumption using a fly-back converter technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,013,167 Hall effect device having voltage based biasing for temperature compensation
A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device...
US-9,013,124 Reverse current protection control for a motor
A method is provided. A command to correspond to a target speed of a motor is received. A rotational speed of the motor is measured, and a brake-to-off ratio...
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