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Patent # Description
US-9,024,384 Indium, carbon and halogen doping for PMOS transistors
A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon...
US-9,023,289 System and method for production of high purity silicon solids and solids therefrom
Systems and methods and resulting compositions of matter including silicon solids from a mixture of silicon and water. The mixture is collected at a collection...
US-9,021,322 Probeless testing of pad buffers on wafer
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US-9,021,320 pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the...
US-9,021,292 Method and system for asynchronous serial communication in a ring network by generating an oversampling clock...
Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial...
US-9,021,283 Processor having real-time power conservation
An apparatus having a processing unit and a monitor for monitoring activity associated with said processing unit. The monitor enables selective lowering of the...
US-9,021,170 System and method for improving ECC enabled memory timing
A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes...
US-9,020,459 Power saving receiver circuits, systems and processes
An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control...
US-9,020,454 Linearization and calibration predistortion of a digitally controlled power amplifier
An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion...
US-9,019,670 Bi-directional ESD protection circuit
A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor...
US-9,019,004 System and method for distributed regulation of charge pumps
A system for providing a load current at a specific voltage to a circuit block of an integrated circuit (IC) includes a plurality of charge pumps and a control...
US-9,018,976 Dual-port positive level sensitive reset preset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch....
US-9,018,923 Dynamic bias soft start control apparatus and methods
Apparatus and methods operate to disable a dynamically biased apparatus and a dynamic bias current source providing dynamic bias current to the apparatus at the...
US-9,018,800 High efficiency wide load range buck/boost/bridge photovoltaic micro-converter
Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the...
US-9,015,544 Accelerating scan test by re-using response data as stimulus data abstract
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-9,015,504 Managing power of thread pipelines according to clock frequency and voltage specified in thread registers
A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions;...
US-9,015,452 Vector math instruction execution by DSP processor approximating division and complex number magnitude
A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication...
US-9,015,376 Method for infrastructure messaging
A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration...
US-9,014,321 Clock drift compensation interpolator adjusting buffer read and write clocks
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming...
US-9,014,305 Bi-phase communication demodulation techniques
One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to...
US-9,014,271 Method and apparatus for region-based weighted prediction with improved global brightness detection
Described herein are a method and apparatus for determining a region-based weighted prediction with improved global brightness detection. The method includes...
US-9,014,247 Communication on a pilot wire
Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). In an...
US-9,014,205 Wireless communications with frequency band selection
A probe, listen and select (PLS) technique can be used to select from an available frequency spectrum a frequency band whose communication quality is suitable...
US-9,013,344 High speed dynamic comparator
A comparator circuit (FIG. 4) is disclosed. The circuit includes an amplifier circuit (300,302) arranged to produce an output signal (Vom,Vop). A first current...
US-9,013,339 Track and hold architecture with tunable bandwidth
To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth...
US-9,013,229 Charge pump circuit
A charge pump circuit includes a plurality of serially coupled stages and a plurality of clock drivers. A voltage output of a first of the stages is connected...
US-9,013,226 Circuits for improving linearity of metal oxide semiconductor (MOS) transistors
Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region...
US-9,013,218 Dual-port negative level sensitive reset data retention latch
In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is...
US-9,013,217 Dual-port negative level sensitive data retention latch
In an embodiment of the invention, a dual-port negative level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked...
US-9,013,203 Tracking energy consumption using a fly-back converter technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,013,167 Hall effect device having voltage based biasing for temperature compensation
A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device...
US-9,013,124 Reverse current protection control for a motor
A method is provided. A command to correspond to a target speed of a motor is received. A rotational speed of the motor is measured, and a brake-to-off ratio...
US-9,013,118 LED control system with a constant reference current
One embodiment includes a light-emitting diode (LED) control system. The system includes an LED driver system configured to regulate a control voltage based on...
US-9,013,032 High pin count, small SON/QFN packages
A plastic SON/QFN package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package;...
US-9,013,028 Integrated circuit package and method of making
An integrated circuit ("IC") device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger...
US-9,011,707 Etching method using an at least semi-solid media
An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively...
US-9,009,554 IC class T0-T2 taps with and without topology selection logic
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
US-9,009,551 Adapter circuitry resetting scan test logic to mandatory feature set
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
US-9,009,550 pBIST engine with distributed data logging
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not...
US-9,009,414 Prefetch address hit prediction to reduce memory access latency
A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined...
US-9,009,408 Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system
This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache...
US-9,008,157 System and method for controlling aberrant transceiver operation
A transceiver and a method of controlling aberrant transceiver operation. In one embodiment, the transceiver includes: (1) a processor, (2) an interrupt system...
US-9,008,124 MAC protocols with subbanding
Systems and methods for designing, using, and/or implementing media access control (MAC) protocols with subbanding are described. In some embodiments, a method...
US-9,008,052 Device for operating using multiple protocols in wireless networks
A network includes an access point using a first protocol and a station using both the first protocol and a second protocol. The station uses the first protocol...
US-9,007,988 Partial CQI feedback in wireless networks
Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an...
US-9,007,334 Baseline capacitance calibration
An embodiment of the invention provides a method of creating a statistical model of a baseline capacitance C.sub.P of a capacitive sensor located on a...
US-9,007,244 Sampling rate based adaptive analog biasing
A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a...
US-9,007,111 Negative edge reset flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable...
US-9,007,091 Dual-port positive level sensitive preset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is...
US-9,006,864 Radiation induced diode structure
A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an...
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