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Patent # Description
US-9,013,032 High pin count, small SON/QFN packages
A plastic SON/QFN package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package;...
US-9,013,028 Integrated circuit package and method of making
An integrated circuit ("IC") device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger...
US-9,011,707 Etching method using an at least semi-solid media
An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively...
US-9,009,554 IC class T0-T2 taps with and without topology selection logic
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
US-9,009,551 Adapter circuitry resetting scan test logic to mandatory feature set
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
US-9,009,550 pBIST engine with distributed data logging
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not...
US-9,009,414 Prefetch address hit prediction to reduce memory access latency
A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined...
US-9,009,408 Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system
This invention handles write request cache misses. The cache controller stores write data, sends a read request to external memory for a corresponding cache...
US-9,008,157 System and method for controlling aberrant transceiver operation
A transceiver and a method of controlling aberrant transceiver operation. In one embodiment, the transceiver includes: (1) a processor, (2) an interrupt system...
US-9,008,124 MAC protocols with subbanding
Systems and methods for designing, using, and/or implementing media access control (MAC) protocols with subbanding are described. In some embodiments, a method...
US-9,008,052 Device for operating using multiple protocols in wireless networks
A network includes an access point using a first protocol and a station using both the first protocol and a second protocol. The station uses the first protocol...
US-9,007,988 Partial CQI feedback in wireless networks
Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an...
US-9,007,334 Baseline capacitance calibration
An embodiment of the invention provides a method of creating a statistical model of a baseline capacitance C.sub.P of a capacitive sensor located on a...
US-9,007,244 Sampling rate based adaptive analog biasing
A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a...
US-9,007,111 Negative edge reset flip-flop with dual-port slave latch
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable...
US-9,007,091 Dual-port positive level sensitive preset data retention latch
In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is...
US-9,006,864 Radiation induced diode structure
A semiconductor device containing an NPN bipolar junction transistor may be formed by forming a p-type radiation induced diode structure (RIDS) region in an...
US-9,006,838 High sheet resistor in CMOS flow
An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with...
US-9,006,833 Bipolar transistor having sinker diffusion under a trench
A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench...
US-9,006,809 Multi-landing contact etching
A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a...
US-9,006,584 High voltage polymer dielectric capacitor isolation device
An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed...
US-9,006,074 High voltage hybrid polymeric-ceramic dielectric capacitor
An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon...
US-9,006,038 Selective leadframe planishing
A method for fabricating a leadframe strip is disclosed. A leadframe pattern is formed from flat sheet of base metal. Additional metal layers are plated on...
US-9,006,001 Simple scatterometry structure for Si recess etch control
Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in...
US-9,005,698 Piezoelectric thin film process
A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity,...
US-9,003,376 Software breakpoints with tailoring for multiple processor shared memory or multiple thread systems
The present invention provides methods for executing instructions in a processor to facilitate the debugging of digital systems. In these methods, a halt...
US-9,003,354 Optimizing memory usage and system performance in a file system requiring entire blocks to be erased for...
A file system which ensures that some of the (desired) files ("linear files") are stored in corresponding exclusive blocks (i.e., a block that stores data...
US-9,003,260 Partial-writes to ECC (error check code) enabled memories
A memory system includes a memory and a memory controller coupled to the memory. The memory controller includes a data buffer configured to store a full data...
US-9,003,250 Compressor inputs from scan register output and input through flip-flop
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device...
US-9,003,249 IC test circuitry with tri-state buffer, comparator, and scan cell
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-9,003,122 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain...
This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines....
US-9,003,096 Serial interface
A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the...
US-9,002,665 Multi-channel flow sensing
A multi-channel flow sensing system typically includes first and second flow-sensing transducers arranged in each channel. A data acquisition system is coupled...
US-9,002,429 Digital drug delivery
For delivery of a chemical to a target region of a subject's brain, an apparatus comprising a storage medium on which is stored digital representations of...
US-9,001,948 Pulse shaping in a communication system
A transmitter used in a communication system includes a raised cosine filter for transmit pulse shaping. A receiver in the communication system, designed to...
US-9,001,928 Transmitter first/second digital predistortion and first/second adaption circuitry with feedback
A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of...
US-9,001,907 Multi-rank precoding matrix indicator (PMI) feedback in a multiple-input multiple-output (MIMO) system
In at least some embodiments, a system includes a multiple-input multiple-output (MIMO) base station and a plurality of MIMO user equipment (UE) devices in...
US-9,001,870 T/R first and second intervals for strobes and data packets
The duration of receiver on-times may be minimized by sensing and reacting to communication channel power levels at intervals. When no energy is detected on the...
US-9,001,844 Overlapping priority contention windows for G3 power line communications networks
Embodiments of methods and systems for overlapping priority contention windows in G3-PLC networks are presented. In one embodiment, a Normal Priority Contention...
US-9,001,756 Physical downlink control channel and physical hybrid automatic repeat request indicator channel enhancements
A wireless transmission system included at least one user equipment and a base station. The base station is operable to form a downlink control information...
US-9,001,712 Transmit signal cancelation apparatus and methods
Apparatus and methods disclosed herein implement an RF receive-band filter at a receive chain input of a wireless base station with a co-located transmitter and...
US-9,001,641 Sounding reference signal processing for LTE
A wireless communication receiver including a serial to parallel converter receiving an radio frequency signal, a fast Fourier transform device connected to...
US-9,001,570 Pseudo retention till access mode enabled memory
A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that...
US-9,001,568 Testing signal development on a bit line in an SRAM
An embodiment of the invention discloses a method for testing a memory cell in an SRAM. The number of dummy memory cells on a single dummy word line used to...
US-9,001,529 System and method for power transfer control based on available input power
The present invention employs system and method in for distinguishing between power capabilities of various external power sources and a system that can...
US-9,001,448 Pre-amplifier output stage with integrated test buffer
Disk drive pre-amplifier output stage circuitry is presented including a high pass input filter for removing DC offsets from differential read data signals and...
US-9,000,980 GNSS receiver correlating doppler derotation samples with code phases
A GNSS receiver includes at least one buffer and at least one correlator block. The at least one buffer stores a plurality of samples corresponding to a...
US-9,000,904 Tire pressure monitoring using half duplex transponder frequency shift
A tire pressure sensor has an RFID (radio frequency identification) device having a parallel resonant circuit including an inductor and a first capacitor for...
US-9,000,897 Systems and methods for implementing application profiles and device classes in power line communication (PLC)...
Systems and methods for application profiles and device classes in power line communications (PLCs) are described. In some embodiments, a PLC device may include...
US-9,000,844 Power efficient transconductance amplifier apparatus and systems
Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed...
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