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Universal filter implementing second-order transfer function
An apparatus includes a biquad filter having first and second lossy integrators and multiple input networks. Each lossy integrator includes an amplifier, and...
Asynchronous clock dividers to reduce on-chip variations of clock timing
This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an...
Electronic device and method for DC-DC conversion with variable bias
The invention relates to an electronic device and a method for DC-DC conversion using a comparator for generating an output signal for driving a power switch of...
System and method for balancing electrical energy storage devices via
differential power bus and capacitive...
System and method are provided for transferring electrical energy among multiple electrical energy storage devices via multiple differential power buses and...
Detection of back EMF in two terminal actuator
Back-emf for a motor is measured by measuring a voltage across the input terminals for a two terminal input actuator or motor when a high frequency driver...
Comparing central time stamp bits from bus and client circuitry
This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined...
Apparatus and method for processing a physical layer convergence protocol
Apparatus and method for processing a physical layer protocol convergence (PLCP) header. In one embodiment, a wireless device includes a PLCP header processor....
Powerline communication frames having CRC within header
A method of powerline communications including a first node and at least a second node on a powerline communications (PLC) channel in a PLC network. The first...
Pairwise temporal key creation for secure networks
A system and method for establishing a pairwise temporal key (PTK) between two devices based on a shared master key and using a single message authentication...
State machine for monitoring a trace port and verifying proper execution
of a secure mode entry sequence...
A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising...
Multi-stage amplifiers to reduce pop noise
An amplifier (50) for voice or audio signals, and particularly for headset applications, uses a low g.sub.m amplifier (54) for initially charging an output node...
IC first, second communication circuits each with three communication
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and...
Signal-to-noise ratio (SNR) dependent channel tracking for smart utility
networks (SUN) orthogonal frequency...
An orthogonal frequency-division multiplexed (OFDM)-based receiver for channel tracking with signal-to-noise ratio dependent parameters that includes a memory;...
Reduction in power supply induced jitter on a SerDes transmitter
In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a...
Changing power to first transmission signals upon detecting ISM band
A method includes transmitting a first set of transmission signals over an operating frequency band. The method includes detecting if a second set of...
Communications in beacon-enabled networks
Systems and methods for designing, using, and/or implementing communications in beacon-enabled networks are described. In various implementations, these systems...
Clock synchronization and distributed guard time provisioning
Embodiments provide a method to accommodate clock drift and guard time in a distributed fashion. A first device is adapted to communicate with a second device....
Enhanced QOS support using Bluetooth low energy
Embodiments support stringent Quality of Service (QoS) requirements using adaptations to the existing Bluetooth Low Energy (BLE) protocols. In systems using an...
Ferroelectric random access memory with isolated power supply during write
and write-back cycles
In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of...
Method for reducing speckle effect in a laser scanning display
Speckle effect in scanning display systems that employs polarized phase-coherent light is reduced by depolarizing the phase-coherent light using a depolarizer...
Enhanced projected image interface
An interactive display projection system, includes a pointing device which determines a location on the projected display indicated by the pointing device using...
DC offset correction with low frequency signal support circuits and
DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a...
Transition mode charge control for a power converter
One embodiment relates to power conversion system. The system includes a converter configured to convert an input voltage to an output voltage, the converter...
Integration of spindle external sense resistor into servo IC with stable
resistance control circuit
An apparatus, comprises three driver FETs coupled at their sources; note-driver circuit; a first sense FET coupled to the sources of the three driver FETs; a...
Semiconductor device with selective planished leadframe
A semiconductor device includes a leadframe, a semiconductor chip, a packaging compound. The leadframe has a pad with straps. Leads on the leadframe include...
Complementary stress memorization technique layer method
A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first...
Flatband shift for improved transistor performance
An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a...
Multi-step deposition of ferroelectric dielectric material
Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical...
Method, system and computer program product for receiving information from
A window is displayed on a display device. The window includes at least first and second portions thereof. In response to a user selecting the first portion of...
Commandable data register control router connected to TCK and TDI
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
Method and system for preventing unauthorized processor mode switches
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing...
Methods and systems involving secure RAM
A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The...
Carrier recovery in amplitude and phase modulated systems
A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q...
PHY payload over multiple tone masks using single tone mask PHY header
A method of powerline communications (PLC) includes compiling a data frame for physical layer (PHY) by a first communications device at a first communications...
Routing protocols for power line communications (PLC)
Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method may include transmitting a one-hop...
High performance two-port SRAM architecture using 8T high performance
single port bit cell
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read...
3D semiconductor interposer for heterogeneous integration of standard
memory and split-architecture processor
A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120)...
Method for generating descriptive trace gaps
A method of managing a debug trace data stream by detecting conditions where the trace data generated exceeds the available transmission bandwidth, and...
System and method for generating 360 degree video recording using MVC
The present invention provides a system and method for combining asymmetrical camera views from a front racing and a back facing camera. Resizing and quality...
Downlink multiple input multiple output enhancements for single-cell with
remote radio heads
A base station selects a subset of at least one geographically separated antennas for each of the plurality of user equipments. The base station forms at least...
Enabling co-existence among power line communication (PLC) technologies
Systems and methods for enabling co-existence among power line communications (PLC) technologies are described. In some embodiments, a method performed by a PLC...
Method and apparatus for a low complexity transform unit partitioning
structure for HEVC
A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining...
Spatially multiplexed pulse width modulation
A process of operating a PWM display system wherein some display data bits are assigned substantially equal time weights. Display data codewords are defined for...
Defect detection in integrated circuit devices
In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the...
Inverting buck-boost using single-inductor boost and charge pump with a
The disclosed methodology for buck-boost inverted voltage conversion uses a boost stage coupled to a charge pump stage at a switch node controlled by a...
Packaged semiconductor device having multilevel leadframes configured as
A semiconductor system (100) has a first planar leadframe (101) with first leads (102) and pads (103) having attached electronic components (120), the first...
Reduced area single poly EEPROM
A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the...
SRAM cell with different crystal orientation than associated logic
An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one...
Electronic assembly with three dimensional inkjet printed traces
One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate...
Integrated circuit for clock generation for memory devices
A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data...